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Do not $mul -> $__mul if A and B are less than maxwidth
Eddie Hung
2019-07-19
1
-1
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+3
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Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold
Eddie Hung
2019-07-19
1
-1
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+1
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Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
Eddie Hung
2019-07-19
1
-28
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+68
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Fine tune ice40_dsp.pmg, add support for packing subsets of registers
Eddie Hung
2019-07-19
4
-35
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+47
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Add support for ice40 signed multipliers
Eddie Hung
2019-07-19
1
-13
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+8
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Merge branch 'xc7dsp' into ice40dsp
Eddie Hung
2019-07-19
1
-1
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+1
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Fix typo in B
Eddie Hung
2019-07-19
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-07-18
29
-228
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+405
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Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp
Eddie Hung
2019-07-19
3
-7
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+239
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ice40: Fix test_dsp_model.sh
David Shah
2019-07-19
1
-1
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+1
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ice40/cells_sim.v: Fix sign of J and K partial products
David Shah
2019-07-19
1
-5
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+7
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ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
David Shah
2019-07-19
1
-2
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+2
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Add tests for all combinations of A and B signedness for comb mul
Eddie Hung
2019-07-19
2
-1
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+229
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Don't copy ref if exists already
Eddie Hung
2019-07-19
1
-1
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+3
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Use sign_headroom instead
Eddie Hung
2019-07-19
1
-4
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+4
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Fix SB_MAC sim model -- do not sign extend internal products?
Eddie Hung
2019-07-18
1
-2
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+2
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Add params
Eddie Hung
2019-07-18
1
-0
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+6
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Merge remote-tracking branch 'origin/master' into ice40dsp
Eddie Hung
2019-07-18
1
-33
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+18
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Merge pull request #1208 from ZirconiumX/intel_cleanups
David Shah
2019-07-18
1
-29
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+14
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synth_intel: Use stringf
Dan Ravensloft
2019-07-18
1
-7
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+2
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synth_intel: s/not family/no family/
Dan Ravensloft
2019-07-18
1
-2
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+2
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synth_intel: revert change to run_max10
Dan Ravensloft
2019-07-18
1
-1
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+1
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intel_synth: Fix help message
Ben Widawsky
2019-07-18
1
-1
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+1
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intel_synth: Small code cleanup to remove if ladder
Ben Widawsky
2019-07-18
2
-29
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+11
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intel_synth: Make family explicit and match
Ben Widawsky
2019-07-18
1
-2
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+6
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intel_synth: Minor code cleanups
Ben Widawsky
2019-07-18
1
-2
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+6
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Merge pull request #1207 from ZirconiumX/intel_new_pass_names
David Shah
2019-07-18
1
-4
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+4
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synth_intel: rename for consistency with #1184
Dan Ravensloft
2019-07-18
1
-4
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+4
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Do not define `DSP_SIGNEDONLY macro if no exists
Eddie Hung
2019-07-18
1
-4
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+3
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Merge remote-tracking branch 'origin/master' into ice40dsp
Eddie Hung
2019-07-18
28
-195
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+387
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Merge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf
2019-07-18
5
-17
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+21
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synth_ecp5: rename dram to lutram everywhere.
whitequark
2019-07-16
4
-13
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+13
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synth_{ice40,ecp5}: more sensible pass label naming.
whitequark
2019-07-16
2
-5
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+9
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Merge pull request #1203 from whitequark/write_verilog-zero-width-values
Clifford Wolf
2019-07-18
1
-1
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+2
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write_verilog: dump zero width constants correctly.
whitequark
2019-07-16
1
-1
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+2
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Remove old $pmux_safe code from write_verilog
Clifford Wolf
2019-07-17
1
-5
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+4
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Merge pull request #1204 from smunaut/fix_1187
David Shah
2019-07-17
2
-4
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+4
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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut
2019-07-16
2
-4
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+4
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Merge pull request #1202 from YosysHQ/cmp2lut_lut6
Eddie Hung
2019-07-16
4
-24
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+37
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gen_lut to return correctly sized LUT mask
Eddie Hung
2019-07-16
1
-1
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+1
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Forgot to commit
Eddie Hung
2019-07-16
1
-0
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+7
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Add tests for cmp2lut on LUT6
Eddie Hung
2019-07-16
2
-23
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+29
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Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
Eddie Hung
2019-07-16
2
-45
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+128
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Add comment
Eddie Hung
2019-07-13
1
-0
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+5
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Update test with more accurate LUT mask
Eddie Hung
2019-07-12
1
-1
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+1
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duplicate -> clone
Eddie Hung
2019-07-12
1
-3
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+3
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More cleanup
Eddie Hung
2019-07-12
1
-8
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+2
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Cleanup
Eddie Hung
2019-07-12
1
-29
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+51
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Cleanup
Eddie Hung
2019-07-12
1
-10
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+4
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Cleanup
Eddie Hung
2019-07-12
1
-15
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+24
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