iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improved support for $sop cells	Clifford Wolf	2016-06-17	2	-4/+4
*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-0/+28
*	Added "nlutmap -assert"	Clifford Wolf	2016-06-09	1	-3/+3
*	Do not run "wreduce" in "prep -ifx"	Clifford Wolf	2016-06-08	1	-2/+3
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	1	-2/+11
*	Added GP_DELAY cell	Andrew Zonenberg	2016-05-07	1	-0/+29
*	Fixed typo in port name	Andrew Zonenberg	2016-05-07	1	-1/+1
*	Fixed extra semicolon	Andrew Zonenberg	2016-05-07	1	-1/+1
*	Fixed typo in parameter name	Andrew Zonenberg	2016-05-07	1	-1/+1
*	Added simulation timescale declaration	Andrew Zonenberg	2016-05-07	1	-0/+2
*	Added synth_ice40 support for latches via logic loops	Clifford Wolf	2016-05-06	3	-0/+13
*	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	Clifford Wolf	2016-05-06	1	-3/+15
*	Changed order of passes for better handling of INIT attributes on "output reg...	Andrew Zonenberg	2016-05-04	1	-2/+2
*	Renamed module parameter	Andrew Zonenberg	2016-05-04	1	-4/+4
*	Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cell...	Andrew Zonenberg	2016-05-04	3	-18/+1
*	Fixed incorrect signal naming in GP_IOBUF	Andrew Zonenberg	2016-05-04	1	-2/+2
*	Added tri-state I/O extraction for GreenPak	Andrew Zonenberg	2016-05-03	5	-2/+29
*	Added GreenPak I/O buffer cells	Andrew Zonenberg	2016-05-03	1	-0/+17
*	Added comment to clarify GP_ABUF cell	Andrew Zonenberg	2016-05-02	1	-0/+2
*	Added GP_ABUF cell	Andrew Zonenberg	2016-05-02	1	-0/+6
*	Added GP_PGA cell	Andrew Zonenberg	2016-04-27	1	-0/+11
*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-24	2	-64/+80
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\| *	Added "prep -flatten" and "synth -flatten"	Clifford Wolf	2016-04-24	2	-7/+36
\| *	Converted "prep" to ScriptPass	Clifford Wolf	2016-04-24	2	-60/+47
* \|	Removed VIN_BUF_EN	Andrew Zonenberg	2016-04-24	1	-1/+0
* \|	Renamed VOUT to OUT on GP_ACMP cell	Andrew Zonenberg	2016-04-23	1	-1/+3
* \|	Added GP_ACMP cell	Andrew Zonenberg	2016-04-23	1	-0/+12
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*	Run clean after splitnets in synth_greenpak4	Clifford Wolf	2016-04-23	1	-1/+1
*	Merge https://github.com/azonenberg/yosys	Clifford Wolf	2016-04-23	1	-1/+7
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\| *	Fixed typo	Andrew Zonenberg	2016-04-22	1	-1/+1
\| *	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-22	9	-12/+12
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\| * \|	Added GP_VREF cell	Andrew Zonenberg	2016-04-20	1	-0/+6
* \| \|	Added "shregmap" to synth_greenpak4	Clifford Wolf	2016-04-23	1	-0/+1
* \| \|	Converted synth_greenpak4 to ScriptPass	Clifford Wolf	2016-04-23	2	-111/+71
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* \|	Added "yosys -D" feature	Clifford Wolf	2016-04-21	9	-12/+12
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*	Added GP_SHREG cell	Andrew Zonenberg	2016-04-13	1	-0/+23
*	Refactoring: alphabetized cells_sim	Andrew Zonenberg	2016-04-13	1	-120/+119
*	Fixed missing semicolon	Andrew Zonenberg	2016-04-09	1	-1/+1
*	Added GP_RCOSC cell	Andrew Zonenberg	2016-04-09	1	-0/+38
*	Fixed assertion failure for non-inferrable counters in some cases	Andrew Zonenberg	2016-04-06	1	-2/+6
*	Added second divider to GP_RINGOSC	Andrew Zonenberg	2016-04-06	1	-8/+13
*	Added GP_RINGOSC primitive	Andrew Zonenberg	2016-04-06	1	-0/+26
*	Added GP_POR	Andrew Zonenberg	2016-04-04	1	-0/+22
*	Added GP_BANDGAP cell	Andrew Zonenberg	2016-04-04	1	-0/+9
*	Removed more debug prints	Andrew Zonenberg	2016-04-01	1	-1/+0
*	Removed forgotten debug code	Andrew Zonenberg	2016-04-01	1	-7/+1
*	Added GreenPak inverter support	Andrew Zonenberg	2016-04-01	3	-4/+13
*	Added support for inferring counters with asynchronous resets. Fixed use-afte...	Andrew Zonenberg	2016-04-01	1	-51/+210
*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-01	5	-225/+153
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\| *	Added ScriptPass helper class for script-like passes	Clifford Wolf	2016-03-31	2	-215/+143