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* A few modifications after pull request commentsRuben Undheim2016-06-183-5/+4
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-187-1/+53
* Added "dc2" to default ABC scriptsClifford Wolf2016-06-171-5/+5
* Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6
* Added "abc -I <num> -P <num>"Clifford Wolf2016-06-171-8/+33
* Added $sop SAT modelClifford Wolf2016-06-171-0/+82
* Improved support for $sop cellsClifford Wolf2016-06-176-10/+89
* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-177-31/+171
* Updated ABC to hg rev b5df6e2b76f0Clifford Wolf2016-06-172-10/+10
* Added "nlutmap -assert"Clifford Wolf2016-06-092-3/+17
* Do not run "wreduce" in "prep -ifx"Clifford Wolf2016-06-081-2/+3
* Added "proc_mux -ifx"Clifford Wolf2016-06-063-21/+54
* Added "setundef -init"Clifford Wolf2016-06-031-5/+89
* Fix all undef-muxes in dlatch input coneClifford Wolf2016-06-021-34/+72
* Avoid creating undef-muxes when inferring latches in proc_dlatchClifford Wolf2016-06-011-0/+44
* Added opt_expr support for div/mod by power-of-twoClifford Wolf2016-05-292-0/+96
* Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}Clifford Wolf2016-05-271-0/+11
* Fixed access-after-delete bug in mem2reg codeClifford Wolf2016-05-272-6/+23
* fixed typos in error messagesClifford Wolf2016-05-271-3/+3
* Fixed "scc" for cells that have feedback singals _and_ are part of a larger loopClifford Wolf2016-05-271-3/+3
* Merge pull request #172 from zeldin/deterministic_hierarchyClifford Wolf2016-05-221-3/+3
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| * Made the expansion order of hierarchy deterministicMarcus Comstedt2016-05-221-3/+3
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* Some fixes in tests/asicworld/*_tb.vClifford Wolf2016-05-204-50/+41
* Improvements and fixes in autotest.sh script and test_autotbClifford Wolf2016-05-202-9/+9
* Merge branch 'master' of https://github.com/Kmanfi/yosysClifford Wolf2016-05-202-11/+18
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| * Close opened dump file.Kaj Tuomi2016-05-191-0/+1
| * Fix for Modelsim transcript line warp issue #164Kaj Tuomi2016-05-192-11/+17
* | Also escape "=" in spice outputClifford Wolf2016-05-201-1/+1
* | Small improvements in Verilog front-end docsClifford Wolf2016-05-202-0/+8
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* Don't sign-extend memory bram initialization dataClifford Wolf2016-05-151-1/+1
* Added missing "#define HASHLIB_H"Clifford Wolf2016-05-141-0/+1
* Minor presentation fixesClifford Wolf2016-05-141-1/+1
* Updated min GCC requirement to GCC 4.8Clifford Wolf2016-05-112-14/+14
* Added manual download link to READMEClifford Wolf2016-05-091-0/+4
* Include <cmath> in yosys.hClifford Wolf2016-05-082-9/+1
* Merge pull request #162 from azonenberg/masterClifford Wolf2016-05-081-2/+33
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| * Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
| * Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
| * Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
| * Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
| * Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
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* Fixes for MXE buildClifford Wolf2016-05-073-10/+10
* Added support for "keep" attribute to shregmapClifford Wolf2016-05-071-2/+2
* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
* Added "write_blif -noalias"Clifford Wolf2016-05-061-6/+26
* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
* Fixed preservation of important attributes in techmapClifford Wolf2016-05-061-4/+32
* Merge pull request #159 from azonenberg/masterClifford Wolf2016-05-055-24/+7
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| * Changed order of passes for better handling of INIT attributes on "output reg...Andrew Zonenberg2016-05-041-2/+2
| * Changed port names in greenpak shregmapAndrew Zonenberg2016-05-041-1/+1
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