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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-04 21:46:07 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-04 21:46:07 -0700 |
| commit | c2b909c051edf189d6e1f807bb367c3c543dc058 (patch) | |
| tree | 3b50288e8e2d0b42644be601bc147d7fb3943603 /techlibs | |
| parent | c01ff05fabe948acfbbb259e92b3bd0009bd068e (diff) | |
| download | yosys-c2b909c051edf189d6e1f807bb367c3c543dc058.tar.gz yosys-c2b909c051edf189d6e1f807bb367c3c543dc058.tar.bz2 yosys-c2b909c051edf189d6e1f807bb367c3c543dc058.zip | |
Added GP_POR
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index d98526215..f013d9b71 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -153,3 +153,25 @@ module GP_BANDGAP(output reg OK, output reg VOUT); //cannot simulate mixed signal IP endmodule + + +module GP_POR(output reg RST_DONE); + parameter POR_TIME = 500; + + initial begin + RST_DONE = 0; + + if(POR_TIME == 4) + #4000; + else if(POR_TIME == 500) + #500000; + else begin + $display("ERROR: bad POR_TIME for GP_POR cell"); + $finish; + end + + RST_DONE = 1; + + end + +endmodule |