Merge https://github.com/cliffordwolf/yosys

9 files changed, 12 insertions, 12 deletions

diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 911737947..255306488 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -120,7 +120,7 @@ struct PrepPass : public Pass {
 
 		bool active = run_from.empty();
 
-		log_header("Executing PREP pass.\n");
+		log_header(design, "Executing PREP pass.\n");
 		log_push();
 
 		if (check_label(active, run_from, run_to, "begin"))
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 8eb1aeba4..acfe888d9 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -132,7 +132,7 @@ struct SynthPass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This comannd only operates on fully selected designs!\n");
 
-		log_header("Executing SYNTH pass.\n");
+		log_header(design, "Executing SYNTH pass.\n");
 		log_push();
 
 		run_script(design, run_from, run_to);
diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc
index 7b5646bf2..998bb73bd 100644
--- a/techlibs/greenpak4/greenpak4_counters.cc
+++ b/techlibs/greenpak4/greenpak4_counters.cc
@@ -408,7 +408,7 @@ struct Greenpak4CountersPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
+		log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
 		
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 8900d8d78..463971d41 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -169,7 +169,7 @@ struct SynthGreenPAK4Pass : public Pass {
 
 		bool active = run_from.empty();
 
-		log_header("Executing SYNTH_GREENPAK4 pass.\n");
+		log_header(design, "Executing SYNTH_GREENPAK4 pass.\n");
 		log_push();
 
 		if (check_label(active, run_from, run_to, "begin"))
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index 8c4b9a37d..db2100381 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -37,7 +37,7 @@ struct Ice40FfinitPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ICE40_FFINIT pass (implement FF init values).\n");
+		log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 9ebc3c0d7..9a6d69df0 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -35,7 +35,7 @@ struct Ice40FfssrPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
+		log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 5730847ce..8b6a23fb2 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -137,7 +137,7 @@ struct Ice40OptPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		string opt_expr_args = "-mux_undef -undriven";
-		log_header("Executing ICE40_OPT pass (performing simple optimizations).\n");
+		log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
 		log_push();
 
 		size_t argidx;
@@ -154,7 +154,7 @@ struct Ice40OptPass : public Pass {
 		{
 			design->scratchpad_unset("opt.did_something");
 
-			log_header("Running ICE40 specific optimizations.\n");
+			log_header(design, "Running ICE40 specific optimizations.\n");
 			for (auto module : design->selected_modules())
 				run_ice40_opts(module);
 
@@ -166,14 +166,14 @@ struct Ice40OptPass : public Pass {
 			if (design->scratchpad_get_bool("opt.did_something") == false)
 				break;
 
-			log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
+			log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n");
 		}
 
 		design->optimize();
 		design->sort();
 		design->check();
 
-		log_header("Finished OPT passes. (There is nothing left to do.)\n");
+		log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");
 		log_pop();
 	}
 } Ice40OptPass;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2ed7642ae..3dbdde3df 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -149,7 +149,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This comannd only operates on fully selected designs!\n");
 
-		log_header("Executing SYNTH_ICE40 pass.\n");
+		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
 
 		run_script(design, run_from, run_to);
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 524fd1d4e..e7ec1e6e8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -160,7 +160,7 @@ struct SynthXilinxPass : public Pass {
 
 		bool active = run_from.empty();
 
-		log_header("Executing SYNTH_XILINX pass.\n");
+		log_header(design, "Executing SYNTH_XILINX pass.\n");
 		log_push();
 
 		if (check_label(active, run_from, run_to, "begin"))