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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-04 16:56:43 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-04 16:56:43 -0700 |
| commit | c01ff05fabe948acfbbb259e92b3bd0009bd068e (patch) | |
| tree | 80e62268dfa7c7b37a7770147c2955cc8e920cdd /techlibs | |
| parent | e4e6becba9259a125bfd2788d453f5ac33272d2f (diff) | |
| download | yosys-c01ff05fabe948acfbbb259e92b3bd0009bd068e.tar.gz yosys-c01ff05fabe948acfbbb259e92b3bd0009bd068e.tar.bz2 yosys-c01ff05fabe948acfbbb259e92b3bd0009bd068e.zip | |
Added GP_BANDGAP cell
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4ea576960..d98526215 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -144,3 +144,12 @@ module GP_SYSRESET(input RST); //cannot simulate whole system reset endmodule + +module GP_BANDGAP(output reg OK, output reg VOUT); + parameter AUTO_PWRDN = 1; + parameter CHOPPER_EN = 1; + parameter OUT_DELAY = 100; + + //cannot simulate mixed signal IP + +endmodule |