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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-06 14:32:32 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-06 14:32:32 +0200 |
| commit | 126da0ad3dfb7b75aaaadc97c7d40b495da9d164 (patch) | |
| tree | 1e9091c8102008da40c80e58dcddee7011609abf /techlibs | |
| parent | aadca148da35963888e362d6eb5a3982b1903c10 (diff) | |
| download | yosys-126da0ad3dfb7b75aaaadc97c7d40b495da9d164.tar.gz yosys-126da0ad3dfb7b75aaaadc97c7d40b495da9d164.tar.bz2 yosys-126da0ad3dfb7b75aaaadc97c7d40b495da9d164.zip | |
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 8b6a23fb2..ae72f5d64 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -static void run_ice40_opts(Module *module) +static void run_ice40_opts(Module *module, bool unlut_mode) { pool<SigBit> optimized_co; vector<Cell*> sb_lut_cells; @@ -84,6 +84,9 @@ static void run_ice40_opts(Module *module) inbits.append(cell->getPort("\\I3")); sigmap.apply(inbits); + if (unlut_mode) + goto remap_lut; + if (optimized_co.count(inbits[0])) goto remap_lut; if (optimized_co.count(inbits[1])) goto remap_lut; if (optimized_co.count(inbits[2])) goto remap_lut; @@ -101,7 +104,7 @@ static void run_ice40_opts(Module *module) cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); cell->unsetParam("\\LUT_INIT"); - cell->setPort("\\A", SigSpec({cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\I3")})); + cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")})); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\I0"); cell->unsetPort("\\I1"); @@ -133,10 +136,15 @@ struct Ice40OptPass : public Pass { log(" opt_clean\n"); log(" while <changed design>\n"); log("\n"); + log("When called with the option -unlut, this command will transform all already\n"); + log("mapped SB_LUT4 cells back to logic.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { string opt_expr_args = "-mux_undef -undriven"; + bool unlut_mode = false; + log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n"); log_push(); @@ -146,6 +154,10 @@ struct Ice40OptPass : public Pass { opt_expr_args += " -full"; continue; } + if (args[argidx] == "-unlut") { + unlut_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -156,7 +168,7 @@ struct Ice40OptPass : public Pass { log_header(design, "Running ICE40 specific optimizations.\n"); for (auto module : design->selected_modules()) - run_ice40_opts(module); + run_ice40_opts(module, unlut_mode); Pass::call(design, "opt_expr " + opt_expr_args); Pass::call(design, "opt_merge"); |