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techlibs
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xilinx
/
cells_sim.v
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Author
Age
Files
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Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
Eddie Hung
2020-01-02
1
-6
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+6
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ifdef __ICARUS__ -> ifndef YOSYS
Eddie Hung
2020-01-01
1
-6
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+6
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ifndef __ICARUS__ -> ifdef YOSYS
Eddie Hung
2020-01-01
1
-2
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+2
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Rework abc9's DSP48E1 model
Eddie Hung
2020-01-01
1
-0
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+79
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Update timings for Xilinx S7 cells
Eddie Hung
2019-12-30
1
-15
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+35
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xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki
2019-12-23
1
-3
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+3
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Add abc9_arrival times for RAM{32,64}M
Eddie Hung
2019-12-20
1
-24
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+10
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xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki
2019-12-19
1
-4
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+197
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xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki
2019-12-18
1
-0
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+35
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RAM64M8 to also have [5:0] for address
Eddie Hung
2019-12-13
1
-8
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+8
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Fix RAM64M model to have 6 bit address bus
Eddie Hung
2019-12-12
1
-4
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+4
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xilinx: Add models for LUTRAM cells. (#1537)
Marcin Kościelnicki
2019-12-04
1
-0
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+797
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xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
1
-0
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+28
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
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+5
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xilinx: Add simulation models for MULT18X18* and DSP48A*.
Marcin Kościelnicki
2019-11-19
1
-0
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+511
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xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki
2019-10-10
1
-0
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+11
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
1
-19
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+19
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
1
-0
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+44
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Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
1
-8
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+44
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Use extractinv for synth_xilinx -ise
Marcin Kościelnicki
2019-09-19
1
-8
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+44
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Mis-spell
Eddie Hung
2019-09-18
1
-10
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+25
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Add pattern detection support for DSP48E1 model, check against vendor
Eddie Hung
2019-09-18
1
-4
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+43
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-05
1
-26
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+70
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Remove trailing space
Eddie Hung
2019-08-30
1
-2
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+2
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-28
1
-15
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+78
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Put attributes above port
Eddie Hung
2019-08-23
1
-19
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+46
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-23
1
-5
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+10
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Add abc_arrival to SRL*
Eddie Hung
2019-08-21
1
-3
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+5
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Oops
Eddie Hung
2019-08-20
1
-1
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+1
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xilinx to use abc_map.v with -max_iter 1
Eddie Hung
2019-08-20
1
-3
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+6
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Add reference to FD* timing
Eddie Hung
2019-08-20
1
-0
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+2
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Remove sequential extension
Eddie Hung
2019-08-20
1
-8
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+16
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Remove SRL* delays from cells_sim.v
Eddie Hung
2019-08-20
1
-5
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+3
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Wrap LUTRAMs in order to capture comb/seq behaviour
Eddie Hung
2019-08-20
1
-15
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+9
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Add LUTRAM delays
Eddie Hung
2019-08-20
1
-3
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+6
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Use abc_{map,unmap,model}.v
Eddie Hung
2019-08-20
1
-8
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+0
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-08-20
1
-2
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+2
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Add arrival times for SRL outputs
Eddie Hung
2019-08-19
1
-3
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+5
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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung
2019-08-30
1
-24
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+79
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Merge branch 'master' into xc7dsp
David Shah
2019-08-30
1
-24
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+91
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
Eddie Hung
2019-08-28
1
-3
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+8
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xilinx: Add SRLC16E primitive.
Marcin Kościelnicki
2019-08-27
1
-1
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+21
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-1
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+1
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Forgot one
Eddie Hung
2019-08-23
1
-1
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+2
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-11
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+22
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Put abc_* attributes above port
Eddie Hung
2019-08-23
1
-7
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+14
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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-14
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+20
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move attributes to wires
Marcin Kościelnicki
2019-08-13
1
-33
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+42
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Add clock buffer insertion pass, improve iopadmap.
Marcin Kościelnicki
2019-08-13
1
-0
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+16
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-08-20
1
-8
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+20
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