diff options
| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-11-24 16:05:45 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-25 20:40:39 +0100 |
| commit | 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d (patch) | |
| tree | 479662c910620126719f95acbd2ab7893496e1ed /techlibs/xilinx/cells_sim.v | |
| parent | 7562e7304e2592ddd5a914ec723a6563c14141e0 (diff) | |
| download | yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.tar.gz yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.tar.bz2 yosys-6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d.zip | |
clkbufmap: Add support for inverters in clock path.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5faddcd52..fa33f4596 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -126,7 +126,11 @@ endmodule // assign O = IO, IO = T ? 1'bz : I; // endmodule -module INV(output O, input I); +module INV( + (* clkbuf_inv = "I" *) + output O, + input I +); assign O = !I; endmodule |