diff options
| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-22 14:30:04 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-23 20:36:43 +0100 |
| commit | dadaf7ed788370c94a463e5e479bed4d540cdf4b (patch) | |
| tree | 3b7ce98de86ecc5a7a0758a784ff81c6f8f94322 /techlibs/xilinx/cells_sim.v | |
| parent | aa1adb0f1e43c353356a8283ad1f2fc007d9f54b (diff) | |
| download | yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.tar.gz yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.tar.bz2 yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.zip | |
xilinx: Test our DSP48A/DSP48A1 simulation models.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 804c2d70f..3bcbfc9aa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2099,7 +2099,7 @@ always @* begin 2'b00: XMUX <= 0; 2'b01: XMUX <= M; 2'b10: XMUX <= P; - 2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT}; + 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; default: XMUX <= 48'hxxxxxxxxxxxx; endcase end @@ -2117,8 +2117,8 @@ end // The post-adder. wire signed [48:0] X_EXT; wire signed [48:0] Z_EXT; -assign X_EXT = XMUX; -assign Z_EXT = ZMUX; +assign X_EXT = {1'b0, XMUX}; +assign Z_EXT = {1'b0, ZMUX}; assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); // Cascade outputs. |