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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-26 05:04:28 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-26 08:15:20 +0100 |
| commit | 0466c48533ad2831a95c6b63c3a190adb76499e9 (patch) | |
| tree | bee4a2fbd4ebc5b0b16877057605b0ae145f2056 /techlibs/xilinx/cells_sim.v | |
| parent | 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d (diff) | |
| download | yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.tar.gz yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.tar.bz2 yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.zip | |
xilinx: Add simulation models for IOBUF and OBUFT.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index fa33f4596..1be43f9d4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -59,6 +59,34 @@ module OBUF( assign O = I; endmodule +module IOBUF ( + (* iopad_external_pin *) + inout IO, + output O, + input I, + input T +); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign IO = T ? 1'bz : I; + assign O = IO; +endmodule + +module OBUFT ( + (* iopad_external_pin *) + output O, + input I, + input T +); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign O = T ? 1'bz : I; +endmodule + module BUFG( (* clkbuf_driver *) output O, |