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* Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-061-51/+59
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+77
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| * \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-21/+41
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| * | | Re-arrange FD orderEddie Hung2019-12-311-77/+77
| * | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-3/+3
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-4/+197
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| * | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-8/+8
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-12/+47
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-0/+797
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| * | | | | | | | Oh deary meEddie Hung2019-12-041-4/+4
| * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-271-0/+28
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-1/+5
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| * \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-191-0/+522
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| * | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-208/+16
| * | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-47/+47
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| * | | | | | | | | | | | More fixesEddie Hung2019-10-011-16/+16
| * | | | | | | | | | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
| * | | | | | | | | | | | Remove need for $currQ port connectionEddie Hung2019-09-301-80/+80
| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-0/+44
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-0/+463
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| * | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
| * | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-47/+247
* | | | | | | | | | | | | | | Fix DSP48E1 simEddie Hung2020-01-061-3/+3
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* | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS tooEddie Hung2020-01-061-0/+2
* | | | | | | | | | | | | | Fix return value of arrival time functions, fix wordEddie Hung2020-01-061-18/+14
* | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactorEddie Hung2020-01-021-6/+6
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| * | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
* | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYSEddie Hung2020-01-011-2/+2
* | | | | | | | | | | | | | Rework abc9's DSP48E1 modelEddie Hung2020-01-011-0/+79
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* | | | | | | | | | | | / Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
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* | | | | | | | | | | | xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-231-3/+3
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* | | | | | | | | | | Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-191-4/+197
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* | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-0/+35
* | | | | | | | | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
* | | | | | | | | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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* | | | | | | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-041-0/+797
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* | | | | | | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-261-0/+28
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* | | | | | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
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* | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-191-0/+511
* | | | | xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-101-0/+11
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* | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-19/+19
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* | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-301-0/+44
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* | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-8/+44
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| * Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-191-8/+44
* | Mis-spellEddie Hung2019-09-181-10/+25
* | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-181-4/+43
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-26/+70
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