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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:25:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:25:34 -0700 |
| commit | 18ebb86edbade4a94833dead59d69fddd980f5bd (patch) | |
| tree | 488827f45c653e2daacc85c1c2ae13f50f241067 /techlibs/xilinx/cells_sim.v | |
| parent | 5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b (diff) | |
| download | yosys-18ebb86edbade4a94833dead59d69fddd980f5bd.tar.gz yosys-18ebb86edbade4a94833dead59d69fddd980f5bd.tar.bz2 yosys-18ebb86edbade4a94833dead59d69fddd980f5bd.zip | |
FDCE_1 does not have IS_CLR_INVERTED
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ee9d48684..cf39bd45b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -408,7 +408,7 @@ module FDCE_1 ( always @* Q = \$nextQ ; `else assign \$currQ = Q; - always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; `endif endmodule |