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* abc9 cleanupEddie Hung2019-02-251-6/+4
* read_aiger to accept empty string for clk_name, passable only if no latchesEddie Hung2019-02-251-2/+1
* abc9 not to clean after aigmapEddie Hung2019-02-251-1/+1
* abc9 to call "clean" once at the end of all abc9_module() callsEddie Hung2019-02-251-4/+4
* abc9 to use AIGER symbol table, as opposed to map fileEddie Hung2019-02-211-5/+16
* Revert "abc9 to write_xaiger -symbols, not -map"Eddie Hung2019-02-211-2/+3
* Remove irrelevant citationsEddie Hung2019-02-211-8/+0
* Add attributionEddie Hung2019-02-211-0/+1
* abc9 to not select anything extra, and pop selection after final cleanEddie Hung2019-02-211-14/+2
* abc9 to write_xaiger -symbols, not -mapEddie Hung2019-02-211-3/+2
* Merge branch 'read_aiger' into xaigEddie Hung2019-02-211-2/+0
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* | abc9 to use &mfsEddie Hung2019-02-211-1/+2
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-218-1/+1202
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| * | Hotfix for 4c82ddfClifford Wolf2019-02-211-11/+2
| * | Add -params mode to force undef parameters in selected cells.Keith Rothman2019-02-211-0/+29
| * | Merge pull request #818 from YosysHQ/clifford/dffsrfixClifford Wolf2019-02-211-6/+7
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| * | | Fix typo in passes/pmgen/README.mdClifford Wolf2019-02-211-1/+1
| * | | Bugfix in ice40_dspClifford Wolf2019-02-211-2/+2
| * | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-4/+4
| * | | Add FF support to wreduceClifford Wolf2019-02-201-1/+70
| * | | Detect and reject cases that do not map well to iCE40 DSPs (yet)Clifford Wolf2019-02-202-2/+17
| * | | Add actual DSP inference to ice40_dsp passClifford Wolf2019-02-173-24/+214
| * | | Merge branch 'master' of github.com:YosysHQ/yosys into pmgenClifford Wolf2019-02-172-1/+8
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| * | | Progress in pmgenClifford Wolf2019-01-151-3/+11
| * | | Progress in pmgen, add pmgen READMEClifford Wolf2019-01-153-14/+260
| * | | Fix pmgen "reject" statementClifford Wolf2019-01-151-1/+1
| * | | Progress in pmgenClifford Wolf2019-01-153-36/+139
| * | | Progress in pmgenClifford Wolf2019-01-153-21/+157
| * | | Progress in pmgenClifford Wolf2019-01-155-8/+347
| * | | Add mockup .pmg (pattern matcher generator) fileClifford Wolf2019-01-151-0/+75
* | | | abc9 to only disconnect output ports of AND and NOT gatesEddie Hung2019-02-211-2/+4
* | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-211-6/+7
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| * | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816Clifford Wolf2019-02-211-6/+7
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* | | ABC -> ABC9Eddie Hung2019-02-201-1/+1
* | | abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_Eddie Hung2019-02-201-21/+29
* | | lut/not/and suffix to be ${lut,not,and}Eddie Hung2019-02-201-4/+4
* | | abc9 to cope with multiple modulesEddie Hung2019-02-201-7/+11
* | | abc9 to use & syntax for -fast, and name fixesEddie Hung2019-02-201-5/+5
* | | abc9 to cope with indexed wires when creating $lut from $_NOT_Eddie Hung2019-02-191-1/+6
* | | abc9 to replace $_NOT_ with $lutEddie Hung2019-02-191-4/+39
* | | Get rid of debugging stuff in abc9Eddie Hung2019-02-161-6/+1
* | | abc9 to write_aiger with -O option, and ignore dummy outputsEddie Hung2019-02-161-2/+8
* | | abc9 to handle comb loops, cope with constant outputs, disconnect using new wireEddie Hung2019-02-161-4/+67
* | | expose command to not skip 'internal' wires beginning with '$'Eddie Hung2019-02-161-1/+1
* | | abc9 to cope with non-wideports, count cells properlyEddie Hung2019-02-161-11/+54
* | | Move lookup inside ifEddie Hung2019-02-151-2/+2
* | | RefactorEddie Hung2019-02-151-29/+32
* | | Cope with width != 1 when re-mapping cellsEddie Hung2019-02-151-11/+25
* | | abc9 to stitch results with CI/CO properlyEddie Hung2019-02-151-16/+32
* | | Fix stitchingEddie Hung2019-02-131-4/+4