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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 13:45:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 13:45:17 -0800 |
| commit | e7c7ab8fc06b3accc7f6d98313ec09e54a605124 (patch) | |
| tree | a458fd6d87293e3b4a8a8387f2b0dee3bece2918 /passes | |
| parent | 8f36013fac34e7cf7b79456f7f8bec8ad6292c99 (diff) | |
| download | yosys-e7c7ab8fc06b3accc7f6d98313ec09e54a605124.tar.gz yosys-e7c7ab8fc06b3accc7f6d98313ec09e54a605124.tar.bz2 yosys-e7c7ab8fc06b3accc7f6d98313ec09e54a605124.zip | |
expose command to not skip 'internal' wires beginning with '$'
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 809345486..3add9a9eb 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -42,7 +42,7 @@ struct dff_map_bit_info_t { bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map) { - if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) + if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name)) return false; if (wire->port_input) return false; |