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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 09:31:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 09:31:17 -0800 |
| commit | be061810d78102eeea79d10f4ff8307bffa34979 (patch) | |
| tree | 2ad28b12ba237302adcf3e934c516018ddecf1dc /passes | |
| parent | 7f26043caf6f9810d8541caaa57151ec8fb539a1 (diff) | |
| parent | 2da4c9c8f0a849434f657ac4a56de11d35e1c41e (diff) | |
| download | yosys-be061810d78102eeea79d10f4ff8307bffa34979.tar.gz yosys-be061810d78102eeea79d10f4ff8307bffa34979.tar.bz2 yosys-be061810d78102eeea79d10f4ff8307bffa34979.zip | |
Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 5880254c1..e8570f0eb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } else { @@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } + + return true; } - else + + if (!hasreset) { IdString new_type; @@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetPort("\\S"); cell->unsetPort("\\R"); - return did_something; + return true; } + + return did_something; } bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) |