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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 14:58:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 14:58:40 -0800 |
| commit | 2811d66dea8a33b6e8440db25d8bf487f70a1dc0 (patch) | |
| tree | 70e5dcb18f5d6253b2c5e91950f54c1f85c1aab5 /passes | |
| parent | 7ad9628f07520c06096971ec09f7ae6f7b4b7b06 (diff) | |
| download | yosys-2811d66dea8a33b6e8440db25d8bf487f70a1dc0.tar.gz yosys-2811d66dea8a33b6e8440db25d8bf487f70a1dc0.tar.bz2 yosys-2811d66dea8a33b6e8440db25d8bf487f70a1dc0.zip | |
Revert "abc9 to write_xaiger -symbols, not -map"
This reverts commit 04429f8152ae64de050580ec20db60ac6dc1c0e1.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 30cd68881..d652ef05a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI @@ -518,7 +518,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool builtin_lib = liberty_file.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); - AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */); + buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols"); + AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */); reader.parse_xaiger(); ifs.close(); |