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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 13:48:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-21 13:49:45 +0100 |
| commit | 2da4c9c8f0a849434f657ac4a56de11d35e1c41e (patch) | |
| tree | 76523ba18f578a753d0830442d17cff6f733e1d0 /passes | |
| parent | 31fea5eb33a5f2feef65b38df869fed217323fb6 (diff) | |
| download | yosys-2da4c9c8f0a849434f657ac4a56de11d35e1c41e.tar.gz yosys-2da4c9c8f0a849434f657ac4a56de11d35e1c41e.tar.bz2 yosys-2da4c9c8f0a849434f657ac4a56de11d35e1c41e.zip | |
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 5880254c1..e8570f0eb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } else { @@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } + + return true; } - else + + if (!hasreset) { IdString new_type; @@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetPort("\\S"); cell->unsetPort("\\R"); - return did_something; + return true; } + + return did_something; } bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) |