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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 14:28:36 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 14:28:36 -0800 |
| commit | 04429f8152ae64de050580ec20db60ac6dc1c0e1 (patch) | |
| tree | bbaad0154aa2e627e7ffd191106ee5dac4ef7abd /passes | |
| parent | 3307295488ee51db20f4a5d911221a1ebc3b8254 (diff) | |
| download | yosys-04429f8152ae64de050580ec20db60ac6dc1c0e1.tar.gz yosys-04429f8152ae64de050580ec20db60ac6dc1c0e1.tar.bz2 yosys-04429f8152ae64de050580ec20db60ac6dc1c0e1.zip | |
abc9 to write_xaiger -symbols, not -map
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index abf0167b5..3eaaa5368 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -414,7 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str())); design->selection_stack.pop_back(); @@ -527,8 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool builtin_lib = liberty_file.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); - buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols"); - AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */); + AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */); reader.parse_xaiger(); ifs.close(); |