| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+25 |
| * | Improvements in assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+16 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -1/+1 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -9/+1 |
| * | Fixed handling of transparent bram rd ports on ROMs | Clifford Wolf | 2016-08-27 | 1 | -0/+1 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+6 |
| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+6 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -8/+17 |
| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -1/+1 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+2 |
| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 1 | -1/+1 |
| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 1 | -0/+9 |
| * | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 1 | -0/+1 |
| * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+31 |
| * | rtlil: speed up SigSpec::sort_and_unify() | Rick Altherr | 2016-01-31 | 1 | -1/+11 |
| * | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -6/+14 |
| * | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+29 |
| * | rtlil: rewrite remove2() to avoid copying | Rick Altherr | 2016-01-30 | 1 | -45/+18 |
| * | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 | 1 | -0/+39 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -14/+14 |
| * | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 | 1 | -12/+11 |
| * | Fixed driver conflict handling (various cmds) | Clifford Wolf | 2015-10-24 | 1 | -3/+12 |
| * | Fixed handling of driver-driver conflicts in wreduce | Clifford Wolf | 2015-10-24 | 1 | -0/+4 |
| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -0/+2 |
| * | Cosmetic fix in Module::addLut() | Clifford Wolf | 2015-09-18 | 1 | -4/+4 |
| * | Added $tribuf and $_TBUF_ cell types | Clifford Wolf | 2015-08-16 | 1 | -0/+20 |
| * | Fixed handling of [a-fxz?] in decimal constants | Clifford Wolf | 2015-08-11 | 1 | -0/+4 |
| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 |
| * | Added design->rename(module, new_name) | Clifford Wolf | 2015-06-30 | 1 | -0/+7 |
| * | Added "rename -top new_name" | Clifford Wolf | 2015-06-17 | 1 | -0/+15 |
| * | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 1 | -1/+1 |
| * | Fixed "avail_parameters" handling in module clone/copy | Clifford Wolf | 2015-06-08 | 1 | -0/+2 |
| * | Added $eq/$neq -> $logic_not/$reduce_bool optimization | Clifford Wolf | 2015-04-29 | 1 | -0/+15 |
| * | Improved attributes API and handling of "src" attributes | Clifford Wolf | 2015-04-24 | 1 | -0/+40 |
| * | Avoid parameter values with size 0 ($mem cells) | Clifford Wolf | 2015-04-05 | 1 | -5/+5 |
| * | Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types | Clifford Wolf | 2015-04-05 | 1 | -0/+4 |
| * | Added $assume cell type | Clifford Wolf | 2015-02-26 | 1 | -0/+7 |
| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 1 | -0/+1 |
| * | Added $meminit cell type | Clifford Wolf | 2015-02-14 | 1 | -0/+9 |
| * | Added SigSpec::has_const() | Clifford Wolf | 2015-02-08 | 1 | -0/+12 |
| * | Added cell->known(), cell->input(portname), cell->output(portname) | Clifford Wolf | 2015-02-07 | 1 | -0/+34 |
| * | Skip blackbox modules in design->selected_modules() | Clifford Wolf | 2015-02-03 | 1 | -3/+5 |
| * | Added "equiv_make -blacklist <file> -encfile <file>" | Clifford Wolf | 2015-01-31 | 1 | -0/+15 |
| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 1 | -0/+30 |
| * | Progress in equiv_simple | Clifford Wolf | 2015-01-21 | 1 | -2/+5 |
| * | Added equiv_make command | Clifford Wolf | 2015-01-19 | 1 | -0/+9 |
| * | Added $equiv cell type | Clifford Wolf | 2015-01-19 | 1 | -0/+8 |
| * | Optimizing no-op cell->setPort() | Clifford Wolf | 2015-01-17 | 1 | -1/+3 |
