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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-27 17:06:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-27 17:06:22 +0200 |
| commit | 23afeadb5e01a7b816c6ae203746caa8ae2aaed7 (patch) | |
| tree | 8565f122de79f622a968ce13d9924499d50caca9 /kernel/rtlil.cc | |
| parent | adcda6817e0df097bf70f8c200edcf15341f3188 (diff) | |
| download | yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.tar.gz yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.tar.bz2 yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.zip | |
Fixed handling of transparent bram rd ports on ROMs
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ad90965fb..72809d42d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1482,6 +1482,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn) log_backtrace("-X- ", yosys_xtrace-1); } + log_assert(GetSize(conn.first) == GetSize(conn.second)); connections_.push_back(conn); } |