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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-21 23:59:58 +0000 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-21 23:59:58 +0000 |
| commit | abf8398216c772bcd23925353f45a17c5d508e8a (patch) | |
| tree | cbade385721e612a2a90d8d4f8238da77f732b43 /kernel/rtlil.cc | |
| parent | 74e1de1facc59665523903e2b2b76e54c44298eb (diff) | |
| download | yosys-abf8398216c772bcd23925353f45a17c5d508e8a.tar.gz yosys-abf8398216c772bcd23925353f45a17c5d508e8a.tar.bz2 yosys-abf8398216c772bcd23925353f45a17c5d508e8a.zip | |
Progress in equiv_simple
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 52293da29..aea993478 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1055,8 +1055,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const log_assert(new_mod->refcount_wires_ == 0); log_assert(new_mod->refcount_cells_ == 0); - new_mod->connections_ = connections_; - new_mod->attributes = attributes; + for (auto &conn : connections_) + new_mod->connect(conn); + + for (auto &attr : attributes) + new_mod->attributes[attr.first] = attr.second; for (auto &it : wires_) new_mod->addWire(it.first, it.second); |