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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-03 23:11:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-03 23:12:23 +0100 |
| commit | 5b41470e151e3b1019e87dfddf900cea51922409 (patch) | |
| tree | 6bb417d8d638c9cfd1d194d3bb48a46243f900bd /kernel/rtlil.cc | |
| parent | 8514fe79dbabb8ed95b24d29e98c16e4027dfc57 (diff) | |
| download | yosys-5b41470e151e3b1019e87dfddf900cea51922409.tar.gz yosys-5b41470e151e3b1019e87dfddf900cea51922409.tar.bz2 yosys-5b41470e151e3b1019e87dfddf900cea51922409.zip | |
Skip blackbox modules in design->selected_modules()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9b55d4255..8c64217bb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -460,7 +460,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_module(it.first)) + if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) result.push_back(it.second); return result; } @@ -470,7 +470,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_whole_module(it.first)) + if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) result.push_back(it.second); return result; } @@ -480,7 +480,9 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_whole_module(it.first)) + if (it.second->get_bool_attribute("\\blackbox")) + continue; + else if (selected_whole_module(it.first)) result.push_back(it.second); else if (selected_module(it.first)) log_warning("Ignoring partially selected module %s.\n", log_id(it.first)); |