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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-17 12:04:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-17 12:04:40 +0100 |
| commit | b32ba6f56802b7cb8bb6098ee895d4ad37438ff8 (patch) | |
| tree | e88d682492d902ccf9fc8e9c2947a3acac7386e5 /kernel/rtlil.cc | |
| parent | 8ce8a230f458d09f1847ba87a3073cf4c07579d3 (diff) | |
| download | yosys-b32ba6f56802b7cb8bb6098ee895d4ad37438ff8.tar.gz yosys-b32ba6f56802b7cb8bb6098ee895d4ad37438ff8.tar.bz2 yosys-b32ba6f56802b7cb8bb6098ee895d4ad37438ff8.zip | |
Optimizing no-op cell->setPort()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d396d6c24..b35cbc3d1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1839,7 +1839,9 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) connections_[portname] = RTLIL::SigSpec(); conn_it = connections_.find(portname); log_assert(conn_it != connections_.end()); - } + } else + if (conn_it->second == signal) + return; for (auto mon : module->monitors) mon->notify_connect(this, conn_it->first, conn_it->second, signal); |