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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-2/+2
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+7
* Small improvements in Verilog front-end docsClifford Wolf2016-05-201-0/+5
* Added manual download link to READMEClifford Wolf2016-05-091-0/+4
* Add instructions for building manual on UbuntuWladimir J. van der Laan2016-04-031-0/+29
* We have 2016 for a while nowClifford Wolf2016-03-301-1/+1
* Link to vlsitechnology.org for liberty filesClifford Wolf2015-11-121-6/+4
* Added examples/ top-level directoryClifford Wolf2015-10-131-1/+1
* Added $finish and $display to READMEClifford Wolf2015-09-181-0/+4
* Switched to Python 3Clifford Wolf2015-08-221-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-10/+10
* Fixed trailing whitespacesClifford Wolf2015-07-021-1/+1
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-241-0/+5
* Added support for initialized xilinx bramsClifford Wolf2015-04-061-1/+1
* Added "keep_hierarchy" attributeClifford Wolf2015-02-251-0/+3
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-0/+5
* Auto-detect TCL versionClifford Wolf2015-02-051-1/+1
* Added onehot attributeClifford Wolf2015-02-041-0/+3
* Minor README changesClifford Wolf2015-02-011-3/+2
* Removed TODO list from README fileClifford Wolf2015-02-011-30/+0
* Added yosys_banner(), Updated Copyright rangeClifford Wolf2015-02-011-1/+1
* README stuffClifford Wolf2015-01-201-2/+3
* Removed psmisc from deps list (usually fuser is already installed and the pac...Clifford Wolf2014-12-141-3/+2
* Added psmisc to prerequisitesClifford Wolf2014-12-121-1/+1
* Added missing prerequisites to READMEClifford Wolf2014-12-121-1/+2
* Improved nomem2reg documentationClifford Wolf2014-10-301-1/+4
* Added support for $readmemh/$readmembClifford Wolf2014-10-261-1/+0
* Added support for "keep" on modulesClifford Wolf2014-09-291-0/+2
* Added "synth" commandClifford Wolf2014-09-141-8/+13
* Removed yosys-svgviewerClifford Wolf2014-09-021-19/+18
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-021-1/+1
* Added DPI-C documentation to README fileClifford Wolf2014-08-221-0/+12
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-221-2/+2
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-0/+27
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-0/+9
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-1/+0
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-041-0/+5
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-2/+1
* Added links to some liberty files to READMEClifford Wolf2014-06-281-0/+8
* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-151-3/+8
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-121-3/+13
* Updated READMEClifford Wolf2014-04-181-18/+11
* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-121-15/+0
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-1/+1
* Updated todo items in README fileClifford Wolf2014-02-051-2/+2
* Added constant size expression support of sized constantsClifford Wolf2014-02-011-0/+4
* Added note about SystemVerilog assert statement to READMEClifford Wolf2014-02-011-0/+5
* Tiny change in example script in READMEClifford Wolf2014-01-291-1/+1
* Fixes and other changes in READMEClifford Wolf2013-12-081-7/+6
* Tighter integration of ABC buildClifford Wolf2013-11-271-4/+2
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