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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-01 13:04:49 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-01 13:04:49 +0100 |
| commit | 1e2440e7ed6979bdee2f80116d6c3a429b604e25 (patch) | |
| tree | bd85ea941530962efb0d51b942e17f3b5dcc0e4c /README | |
| parent | fa92722358f156a1e4b99d3ba4e0900e0a771116 (diff) | |
| download | yosys-1e2440e7ed6979bdee2f80116d6c3a429b604e25.tar.gz yosys-1e2440e7ed6979bdee2f80116d6c3a429b604e25.tar.bz2 yosys-1e2440e7ed6979bdee2f80116d6c3a429b604e25.zip | |
Added note about SystemVerilog assert statement to README
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -270,6 +270,11 @@ Verilog Attributes and non-standard features for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- The "assert" statement from SystemVerilog is supported in its most basic + form. In module context: "assert property (<expression>);" and within an + always block: "assert(<expression>);". It is transformed to a $assert cell + that is supported by the "sat" and "write_btor" commands. + Workarounds for known build problems ==================================== |