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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
| commit | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (patch) | |
| tree | d1a4bb9dfe62ac911ca4751a98b3b63dba22af40 /README | |
| parent | 6ca0c569d92883b6eac1725204de90aee4af31bc (diff) | |
| download | yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.gz yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.bz2 yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.zip | |
Renamed "stdcells.v" to "techmap.v"
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -304,8 +304,7 @@ Roadmap / Large-scale TODOs - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Technology mapping for real-world applications - - Add bit-wise const-folding via cell parameters to techmap pass - - Rewrite current stdcells.v techmap rules (modular and clean) + - Rewrite current techmap.v rules (modular and clean) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Implement SAT-based formal equivialence checker |