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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-01 13:50:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-01 13:50:23 +0100 |
| commit | d06258f74f724ea3ed26ec9341dd64a51e320ccf (patch) | |
| tree | cb0a5af86db1dff05686490bdb1ed5908471d2e2 /README | |
| parent | 1e2440e7ed6979bdee2f80116d6c3a429b604e25 (diff) | |
| download | yosys-d06258f74f724ea3ed26ec9341dd64a51e320ccf.tar.gz yosys-d06258f74f724ea3ed26ec9341dd64a51e320ccf.tar.bz2 yosys-d06258f74f724ea3ed26ec9341dd64a51e320ccf.zip | |
Added constant size expression support of sized constants
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -275,6 +275,10 @@ Verilog Attributes and non-standard features always block: "assert(<expression>);". It is transformed to a $assert cell that is supported by the "sat" and "write_btor" commands. +- Sized constants (the syntax <size>'s?[bodh]<value>) support constant + expressions as <size>. If the expresion is not a simple identifier, it + must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 + Workarounds for known build problems ==================================== |