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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-06 15:43:46 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-06 15:52:54 +0200 |
| commit | d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f (patch) | |
| tree | 86c90432e4453f030be99a5e30a4c9d10ef53d62 /README | |
| parent | b4f10e342cf400bd2f392a588f28de069ba0f9d8 (diff) | |
| download | yosys-d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f.tar.gz yosys-d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f.tar.bz2 yosys-d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f.zip | |
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Diffstat (limited to 'README')
| -rw-r--r-- | README | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -326,7 +326,6 @@ Other Unsorted TODOs - Implement missing Verilog 2005 features: - - Multi-dimensional arrays - Support for real (float) const. expressions and parameters - ROM modeling using $readmemh/$readmemb in "initial" blocks - Ignore what needs to be ignored (e.g. drive and charge strengths) |