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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-13 13:03:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-13 13:03:38 +0200 |
| commit | f53984795d38946ee71684d88883cafd9f58f603 (patch) | |
| tree | 21aff3aeacec725c3f7ff1eea59561955e735e50 /README | |
| parent | 9d353fc543295db7d6f4b4ba60c2b66a509b3ee2 (diff) | |
| download | yosys-f53984795d38946ee71684d88883cafd9f58f603.tar.gz yosys-f53984795d38946ee71684d88883cafd9f58f603.tar.bz2 yosys-f53984795d38946ee71684d88883cafd9f58f603.zip | |
Added support for non-standard """ macro bodies
Diffstat (limited to 'README')
| -rw-r--r-- | README | 9 |
1 files changed, 9 insertions, 0 deletions
@@ -281,6 +281,15 @@ Verilog Attributes and non-standard features to simply declare a module port as 'input' or 'output' in the module body. +- When defining a macro with `define, all text between tripple double quotes + is interpreted as macro body, even if it contains unescaped newlines. The + tripple double quotes are removed from the macro body. For example: + + `define MY_MACRO(a, b) """ + assign a = 23; + assign b = 42; + """ + - Sized constants (the syntax <size>'s?[bodh]<value>) support constant expressions as <size>. If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 |