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* libxc: introduce xc_domain_get_guest_width()Dario Faggioli2013-09-131-5/+3
| | | | | | | | | | | | | | As a wrapper to XEN_DOMCTL_get_address_size, and use it wherever the call was being issued directly via do_domctl(), saving quite some line of code. Actually, the function returns the guest width in bytes, rather than directly what XEN_DOMCTL_get_address_size provides (which is a number of bits), since that is what it is useful almost everywhere. Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* libxc: check return values from mallocIan Jackson2013-06-141-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A sufficiently malformed input to libxc (such as a malformed input ELF or other guest-controlled data) might cause one of libxc's malloc() to fail. In this case we need to make sure we don't dereference or do pointer arithmetic on the result. Search for all occurrences of \b(m|c|re)alloc in libxc, and all functions which call them, and add appropriate error checking where missing. This includes the functions xc_dom_malloc*, which now print a message when they fail so that callers don't have to do so. The function xc_cpuid_to_str wasn't provided with a sane return value and has a pretty strange API, which now becomes a little stranger. There are no in-tree callers. This is part of the fix to a security issue, XSA-55. Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> v8: Move a check in xc_exchange_page to the previous patch (ie, remove it from this patch). v7: Add a missing check for a call to alloc_str. Add arithmetic overflow check in xc_dom_malloc. Coding style fix. v6: Fix a missed call `pfn_err = calloc...' in xc_domain_restore.c. Fix a missed call `new_pfn = xc_map_foreign_range...' in xc_offline_page.c v5: This patch is new in this version of the series.
* x86: Expose TSC adjust to HVM guestLiu, Jinsong2012-09-261-1/+2
| | | | | | | | | | Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. This patch expose it to hvm guest. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86,tools/libxc: expose HLE/RTM features to pv and hvmLiu, Jinsong2012-03-011-0/+4
| | | | | | | | | Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to pv and hvm Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* x86/AMD: Add support for AMD's OSVW feature in guests.Boris Ostrovsky2012-02-071-0/+1
| | | | | | | | | | | | | | | | | | In some cases guests should not provide workarounds for errata even when the physical processor is affected. For example, because of erratum 400 on family 10h processors a Linux guest will read an MSR (resulting in VMEXIT) before going to idle in order to avoid getting stuck in a non-C0 state. This is not necessary: HLT and IO instructions are intercepted and therefore there is no reason for erratum 400 workaround in the guest. This patch allows us to present a guest with certain errata as fixed, regardless of the state of actual hardware. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Acked-by: Christoph Egger <Christoph.Egger@amd.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Jan Beulich <jbeulich@suse.com>
* X86: Prepare PCID/INVPCID for hvmLiu, Jinsong2011-12-061-0/+2
| | | | | | | | | | This patch is used to prepare exposing PCID/INVPCID features to hvm guest. The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* X86: Disable PCID/INVPCID for pvLiu, Jinsong2011-12-061-0/+1
| | | | | | | This patch disable PCID/INVPCID for pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* X86: expose Intel new features to pv/hvmLiu, Jinsong2011-12-061-4/+13
| | | | | | | | | | Intel recently release some new features, including FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE. Refer to http://software.intel.com/file/36945 This patch expose these new features to pv and hvm. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* tools/libxc: Fix x86_32 build breakage in previous changeset.Keir Fraser2011-12-021-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* tools/x86_64: Fix cpuid() inline asm to not clobber stack's red zoneKeir Fraser2011-12-021-9/+9
| | | | | | | | | | Pushing stuff onto the stack on x86-64 when we do not specify -mno-red-zone is unsafe. Since the complicated asm is due to register pressure on i386, we simply implement an all-new simpler alternative for x86-64. Signed-off-by: Keir Fraser <keir@xen.org> Acked-by: Jan Beulich <jbeulich@novell.com>
* xen: provide pse36 cpuid bitTim Deegan2011-11-031-3/+7
| | | | | | | | | | | Provide pse36 cpuid bit if guest runs in 32bit PAE or in long mode. Hyper-V refuses to start as the "cpu does not provide required hw features" if it does not find the pse36 cpuid bits. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Tim Deegan <tim@xen.org>
* libxc: Enable cpuid performance counter leaf for HVMJuergen Gross2011-09-151-0/+1
| | | | | | | | In HVM domains the usable performance counters can be checked automatically only, if cpuid leaf 0x0000000a is accessible. Signed-off-by: Juergen Gross <juergen.gross@ts.fujitsu.com> Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
* nestedsvm: Support TSC Rate MSRChristoph Egger2011-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | Support TSC Rate MSR and enable TSC scaling for nested virtualization. With it, guest VMs don't need take #VMEXIT to calculate a translated TSC value when it is running under TSC emulation mode. I measured native performance of the rdtsc instruction in the l2 guest with xen-on-xen and both host and and l1 guest run under TSC emulation mode. TSC scaling just needs MSR emulation and correct tsc offset calculation to be done and thus can be emulated also on older hardware. In this case rdtsc instruction is intercepted and handled by the host directly and safes the cost of a full VMRUN/VMEXIT emulation cycle. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* xen/libxc: Clean up pv_cpuid switch statements.Keir Fraser2011-07-161-5/+5
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* xen/libxc: set CPUID topology leaf as unsupported for PV guestsDavid Vrabel2011-07-161-0/+1
| | | | | | | | | | | | | | | The result of a CPUID Extended Topology Enumeration leaf for PV guests is invalid as the level in ECX is ignored. This can cause some guests to loop endlessly when trying to enumerate the topology. Since the physical topology isn't useful to PV guests set the topology leaf as unsupported. Guests affected include Linux kernels prior 2.6.32 where a workaround was applied ("xen: mask extended topology info in cpu", 82d6469916c6fcfa345636a49004c9d1753905d1). Signed-off-by: David Vrabel <david.vrabel@citrix.com>
* Enable RDWRGSFS feature support for HVM guestsYang, Wei2011-06-151-1/+2
| | | | | | | Write/read FS/GS base instructions enable user level code to read/write FS & GS segment base registers for thread local storage. Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
* x86: Pass through ERMS CPUID feature for HVM and PV guestsYang, Wei2011-06-141-2/+4
| | | | | | | | | This patch exposes ERMS feature to HVM and PV guests. The REP MOVSB/STOSB instruction can enhance fast strings attempts to move as much of the data with larger size load/stores as possible. Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
* x86/hvm: Make DRNG feature visible in CPUIDYang, Wei2011-06-141-0/+1
| | | | | | | | | This patch exposes DRNG feature to HVM guests. The RDRAND instruction can provide software with sequences of random numbers generated from white noise. Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
* x86/hvm: add SMEP support to HVM guestTim Deegan2011-06-061-0/+8
| | | | | | | | | | | | | | | Intel new CPU supports SMEP (Supervisor Mode Execution Protection). SMEP prevents software operating with CPL < 3 (supervisor mode) from fetching instructions from any linear address with a valid translation for which the U/S flag (bit 2) is 1 in every paging-structure entry controlling the translation for the linear address. This patch adds SMEP support to HVM guest. Signed-off-by: Yang Wei <wei.y.yang@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Li Xin <xin.li@intel.com> Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* nestedsvm: Support DecodeassistChristoph Egger2011-06-081-1/+2
| | | | | | Offer l1 guest to use decode assist if available in hardware. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* libxc: Simplify and clean up xc_cpufeature.hKeir Fraser2011-06-021-3/+3
| | | | | | | | * Remove Linux-private defns with no direct relation to CPUID * Remove word offsets into Linux-defined cpu_caps array * Hard tabs -> soft tabs Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Hide CPUID leaf 7 from PV guests.Keir Fraser2011-06-021-1/+9
| | | | | | Except for the whitelisted FSGSBASE feature. Signed-off-by: Keir Fraser <keir@xen.org>
* x86/LWP: export LWP related CPUID to AMD SVM guestWei Huang2011-05-091-2/+4
| | | | | | This patch exposes LWP CPUID 0x8000001C to SVM guests. Signed-off-by: Wei Huang <wei.huang2@amd.com>
* libxc: Fill in XSAVE-related CPUID leaves for PV guests.Keir Fraser2011-04-251-4/+10
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* tools: Add nestedhvm guest config optioncegger2011-02-281-9/+66
| | | | | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Tim Deegan <Tim.Deegan@citrix.com> Committed-by: Tim Deegan <Tim.Deegan@citrix.com>
* hvm: allow pass-through of new FPU/ALU CPUID featuresKeir Fraser2011-01-271-1/+6
| | | | | | | | | there are some new CPUID features that are safe for guests to see, as they don't require OS awareness (FPU/ALU related instructions only). Among features for new AMD CPUs there is also the PCLMULQDQ bit, which Intel CPU have already for quite a while. Signed-off-by: Andre Przywara <andre.przywara@amd.com>
* x86: blacklist new AMD CPUID bits for PV domainsKeir Fraser2011-01-261-0/+5
| | | | | | | | | | | | there are some new CPUID bits (and leaves) which Dom0 and PV domains should not see to avoid trouble, since we don't emulate the features. The most prominent one is a topology leaf, which contains information specific to the physical CPU, not the virtual one. To avoid confusion (and possibly crashes) due to a confused Dom0 scheduler simply disable these bits. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Keir Fraser <keir@xen.org>
* libxc: Update AMD CPU feature flags 0x80000001:ECX for Xen toolsKeir Fraser2011-01-081-3/+3
| | | | | | | This patch syncs-up AMD CPU feature flags 0x80000001:ECX in libxc with the latest Linux kernel. Signed-off-by: Wei Huang <wei.huang2@amd.com>
* x86 xsave: supports xsave (CPUID:0xD) enumeration for all sub-leaves.Keir Fraser2010-12-241-48/+64
| | | | | | | | | | | | | | | | In specific, it fixes the following issues: 1. The sub-leaves of CPUID:0x0000000D aren't contiguous. Hypervisor shouldn't use register values to stop the enumeration. This patch moves checking on XSAVE sub-leaves out of if-else statement. It also bumps up sub-leaves to 63. 2. It creates a common function for xsave. 3. The main leaf 0 of CPUID:0x0000000D in current Xen is broken, especially ECX and EBX registers. This patch cleans it up. 4. It adds support to detects EBX value of CPUID:0x0000000D main leaf 0 on-the-fly. Signed-off-by: Wei Huang2 <wei.huang2@amd.com>
* x86 hvm: Move CPUID.0xd (XSAVE) configuration into libxc.Keir Fraser2010-12-171-4/+53
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86 hvm: Expose TSC_DEADLINE CPU feature to guests via CPUID.Keir Fraser2010-12-151-0/+1
| | | | Signed-off-by: Wei Gang <gang.wei@intel.com>
* Fix xc_cpuid_hvm_policy to avoid guest CPUID feature missing.Keir Fraser2010-12-091-2/+2
| | | | Signed-off-by: Wei Gang <gang.wei@intel.com>
* x86 hvm: x2APIC emulationKeir Fraser2010-12-071-1/+2
| | | | | | | | | | | This patch would enable Xen to handle x2APIC MSR accessing of HVM guest, which is faster(avoid decoding of MMIO accessing). The credit comes to Gleb Natapov who complete the work for KVM. Have tested with 4 vcpus guest, with/without x2apic support. From: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x86 xsave: Adding back CPUID support for Xsave (version 2)Keir Fraser2010-11-151-4/+26
| | | | | | XSave support via CPUID virtualization for both PV and HVM guests. Signed-off-by: Shan Haitao <haitao.shan@intel.com>
* x86: Do not expose XSAVE/AVX to guests.Keir Fraser2010-11-041-2/+2
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86 hvm: exposes AVX to guest.Keir Fraser2010-11-031-1/+2
| | | | | Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Han Weidong <weidong.han@intel.com>
* x86: Xsave support for PV guests.Keir Fraser2010-11-031-1/+0
| | | | | Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Han Weidong <weidong.han@intel.com>
* # HG changeset patchIan Campbell2010-08-241-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | # User Ian Campbell <ian.campbell@citrix.com> # Date 1282671421 -3600 # Node ID d1dd29a470ef1b9d2c77478a123326036dfe90bb # Parent d7a4adad9c328decbd384d87b23001aea8951b86 tools/libxc, tools/libelf: Relicense under LGPL v2.1 Relicense these two libraries under LGPL v2.1 only except where individual files already included the "or later" provision. Copyright holders have been contacted by Stephen Spector and have all agreed this change. Removed tools/libxc/ia64/aclinux.h since it appeared to be unused. There is a separate, more up to date, copy in xen/include/acpi/platform/aclinux.h which does appear to be used. Clarify the license of MiniOS privcmd.h under the same terms as other tools/include/xen-sys headers. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stephen Spector <stephen.spector@citrix.com> Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
* libxc: eliminate static variables, use xentoollog; API changeKeir Fraser2010-05-281-26/+31
| | | | | | | | | | | | | | | | | | | | This patch eliminate the global variables in libxenctrl (used for logging and error reporting). Instead the information which was in the global variables is now in a new xc_interface* opaque structure, which xc_interface open returns instead of the raw file descriptor; furthermore, logging is done via xentoollog. There are three new parameters to xc_interface_open to control the logging, but existing callers can just pass "0" for all three to get the old behaviour. All libxc callers have been adjusted accordingly. Also update QEMU_TAG for corresponding qemu change. Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
* hvm: Extend the CPUID whitelist to include Intel's AES-NI intructionsKeir Fraser2010-05-261-1/+2
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* libxc: Fix cpuid() inline asm.Keir Fraser2010-02-241-4/+13
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* HVM RDTSCP fixesKeir Fraser2009-12-161-1/+2
| | | | | | | - Put the guest rdtscp cpuid logic in xc_cpuid_x86.c. - MSR_TSC_AUX's high 32bit is reserved, so only write the low 32bit. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
* x86, hvm: Make host TscInvariant CPUID flag visible to guest by default.Keir Fraser2009-11-091-0/+8
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vmx: add the support of XSAVE/XRSTOR to VMX guestKeir Fraser2009-09-291-1/+1
| | | | | | | | | | | | | | | XSAVE/XRSTOR manages the existing and future processor extended states on x86 architecture. The XSAVE/XRSTOR infrastructure is defined in Intel SDMs: http://www.intel.com/products/processor/manuals/ The patch uses the classical CR0.TS based algorithm to manage the states on context switch. At present, we know 3 bits in the XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX Programming Reference: http://software.intel.com/sites/avx/ Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* x86 hvm: Remove vendor-specific feature masking of 0x1:ECX.Keir Fraser2009-08-191-12/+0
| | | | | | Vendors are respecting each others bits. Signed-off-by: Andre Przywara <andre.przywara@amd.com>
* x86: Mask X86_FEATURE_XSAVE in cpuid leaf 1, ecx, as we don't allowKeir Fraser2009-03-091-0/+1
| | | | | | | | | | guests to use it (by setting cr4.OSXSAVE). This prevents crashes in pvops kernels, as new versions of Linux try to use this feature. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: support CPUID hypervisor feature bitKeir Fraser2008-11-191-0/+3
| | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: Expose host core/HT topology to HVM guests.Keir Fraser2008-09-301-4/+30
| | | | | Based on an initial patch by Nitin Kamble <nitin.a.kamble@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, amd, hvm: pass through one more cpuid cache description leafKeir Fraser2008-09-181-6/+11
| | | | | | | | | Add a missing CPUID leaf that contains AMD-specific cache info. Without this, Windows can spin trying to prefetch memory buffers using a stride length of zero. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: cpuid configuration for PV guestKeir Fraser2008-06-111-39/+136
| | | | | | | | | | | | Add pv guest support for the cpuid configuration and checking. That feature only works for cpuid request which are coming from the guest's kernel, a process could still call the cpuid directly. A new policy for pv guest has been created in libxc. dom0 cpuid emulation is left hardcoded in Xen. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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