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| author | Keir Fraser <keir.fraser@citrix.com> | 2008-09-30 10:14:54 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2008-09-30 10:14:54 +0100 |
| commit | ca2eee92df441231adfc3b8f5160d0bf8053c6d1 (patch) | |
| tree | fce7b58b6bb9ecd9c01e68f853e5321d0bac167b /tools/libxc/xc_cpuid_x86.c | |
| parent | 3321e0ef95291a7b07dc30b68f822d69fc10bcb0 (diff) | |
| download | xen-ca2eee92df441231adfc3b8f5160d0bf8053c6d1.tar.gz xen-ca2eee92df441231adfc3b8f5160d0bf8053c6d1.tar.bz2 xen-ca2eee92df441231adfc3b8f5160d0bf8053c6d1.zip | |
x86, hvm: Expose host core/HT topology to HVM guests.
Based on an initial patch by Nitin Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Diffstat (limited to 'tools/libxc/xc_cpuid_x86.c')
| -rw-r--r-- | tools/libxc/xc_cpuid_x86.c | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index 9a1aa89699..6a8e7594c8 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -92,6 +92,7 @@ static void amd_xc_cpuid_policy( /* Filter all other features according to a whitelist. */ regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) | + bitmaskof(X86_FEATURE_CMP_LEGACY) | bitmaskof(X86_FEATURE_ALTMOVCR) | bitmaskof(X86_FEATURE_ABM) | bitmaskof(X86_FEATURE_SSE4A) | @@ -108,6 +109,14 @@ static void amd_xc_cpuid_policy( bitmaskof(X86_FEATURE_3DNOWEXT)); break; } + + case 0x80000008: + /* + * ECX[15:12] is ApicIdCoreSize: ECX[7:0] is NumberOfCores (minus one). + * Update to reflect vLAPIC_ID = vCPU_ID * 2. + */ + regs[2] = ((regs[2] & 0xf000u) + 1) | ((regs[2] & 0xffu) << 1) | 1u; + break; } } @@ -123,8 +132,13 @@ static void intel_xc_cpuid_policy( break; case 0x00000004: - regs[0] &= 0x3FF; - regs[3] &= 0x3FF; + /* + * EAX[31:26] is Maximum Cores Per Package (minus one). + * Update to reflect vLAPIC_ID = vCPU_ID * 2. + */ + regs[0] = (((regs[0] & 0x7c000000u) << 1) | 0x04000000u | + (regs[0] & 0x3ffu)); + regs[3] &= 0x3ffu; break; case 0x80000001: { @@ -141,6 +155,11 @@ static void intel_xc_cpuid_policy( case 0x80000005: regs[0] = regs[1] = regs[2] = 0; break; + + case 0x80000008: + /* Mask AMD Number of Cores information. */ + regs[2] = 0; + break; } } @@ -162,6 +181,12 @@ static void xc_cpuid_hvm_policy( break; case 0x00000001: + /* + * EBX[23:16] is Maximum Logical Processors Per Package. + * Update to reflect vLAPIC_ID = vCPU_ID * 2. + */ + regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1); + regs[2] &= (bitmaskof(X86_FEATURE_XMM3) | bitmaskof(X86_FEATURE_SSSE3) | bitmaskof(X86_FEATURE_CX16) | @@ -189,7 +214,8 @@ static void xc_cpuid_hvm_policy( bitmaskof(X86_FEATURE_MMX) | bitmaskof(X86_FEATURE_FXSR) | bitmaskof(X86_FEATURE_XMM) | - bitmaskof(X86_FEATURE_XMM2)); + bitmaskof(X86_FEATURE_XMM2) | + bitmaskof(X86_FEATURE_HT)); /* We always support MTRR MSRs. */ regs[3] |= bitmaskof(X86_FEATURE_MTRR); @@ -211,7 +237,7 @@ static void xc_cpuid_hvm_policy( case 0x80000008: regs[0] &= 0x0000ffffu; - regs[1] = regs[2] = regs[3] = 0; + regs[1] = regs[3] = 0; break; case 0x00000002: /* Intel cache info (dumped by AMD policy) */ |