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| author | Keir Fraser <keir.fraser@citrix.com> | 2009-09-29 11:27:53 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2009-09-29 11:27:53 +0100 |
| commit | fb7925518f22199dd55fb3e204fb609affe7f4cd (patch) | |
| tree | 2372678883881b2d8574e4de9b71b2560df29264 /tools/libxc/xc_cpuid_x86.c | |
| parent | 341c0e113f2b60c37813708cd91f4507ed08f3f4 (diff) | |
| download | xen-fb7925518f22199dd55fb3e204fb609affe7f4cd.tar.gz xen-fb7925518f22199dd55fb3e204fb609affe7f4cd.tar.bz2 xen-fb7925518f22199dd55fb3e204fb609affe7f4cd.zip | |
vmx: add the support of XSAVE/XRSTOR to VMX guest
XSAVE/XRSTOR manages the existing and future processor extended states
on x86 architecture.
The XSAVE/XRSTOR infrastructure is defined in Intel SDMs:
http://www.intel.com/products/processor/manuals/
The patch uses the classical CR0.TS based algorithm to manage the
states on context switch. At present, we know 3 bits in the
XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX
Programming Reference: http://software.intel.com/sites/avx/
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
Diffstat (limited to 'tools/libxc/xc_cpuid_x86.c')
| -rw-r--r-- | tools/libxc/xc_cpuid_x86.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index f31066a460..90fab3906c 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -28,7 +28,7 @@ #define clear_bit(idx, dst) ((dst) &= ~(1u << ((idx) & 31))) #define set_bit(idx, dst) ((dst) |= (1u << ((idx) & 31))) -#define DEF_MAX_BASE 0x00000004u +#define DEF_MAX_BASE 0x0000000du #define DEF_MAX_EXT 0x80000008u static int hypervisor_is_64bit(int xc) |