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* x86: Expose TSC adjust to HVM guestLiu, Jinsong2012-09-261-0/+1
| | | | | | | | | | Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. This patch expose it to hvm guest. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86,tools/libxc: expose HLE/RTM features to pv and hvmLiu, Jinsong2012-03-011-0/+2
| | | | | | | | | Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to pv and hvm Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* X86: Disable PCID/INVPCID for pvLiu, Jinsong2011-12-061-0/+2
| | | | | | | This patch disable PCID/INVPCID for pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* X86: expose Intel new features to pv/hvmLiu, Jinsong2011-12-061-0/+5
| | | | | | | | | | Intel recently release some new features, including FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE. Refer to http://software.intel.com/file/36945 This patch expose these new features to pv and hvm. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* x86: Pass through ERMS CPUID feature for HVM and PV guestsYang, Wei2011-06-141-0/+1
| | | | | | | | | This patch exposes ERMS feature to HVM and PV guests. The REP MOVSB/STOSB instruction can enhance fast strings attempts to move as much of the data with larger size load/stores as possible. Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
* x86/hvm: Make DRNG feature visible in CPUIDYang, Wei2011-06-141-0/+1
| | | | | | | | | This patch exposes DRNG feature to HVM guests. The RDRAND instruction can provide software with sequences of random numbers generated from white noise. Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
* x86/hvm: add SMEP support to HVM guestTim Deegan2011-06-061-0/+1
| | | | | | | | | | | | | | | Intel new CPU supports SMEP (Supervisor Mode Execution Protection). SMEP prevents software operating with CPL < 3 (supervisor mode) from fetching instructions from any linear address with a valid translation for which the U/S flag (bit 2) is 1 in every paging-structure entry controlling the translation for the linear address. This patch adds SMEP support to HVM guest. Signed-off-by: Yang Wei <wei.y.yang@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Li Xin <xin.li@intel.com> Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* libxc: Don't refer to meaningless 'word offsets' in xc_cpufeature.hKeir Fraser2011-06-031-6/+6
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* libxc: Simplify and clean up xc_cpufeature.hKeir Fraser2011-06-021-114/+95
| | | | | | | | * Remove Linux-private defns with no direct relation to CPUID * Remove word offsets into Linux-defined cpu_caps array * Hard tabs -> soft tabs Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Hide CPUID leaf 7 from PV guests.Keir Fraser2011-06-021-0/+3
| | | | | | Except for the whitelisted FSGSBASE feature. Signed-off-by: Keir Fraser <keir@xen.org>
* hvm: allow pass-through of new FPU/ALU CPUID featuresKeir Fraser2011-01-271-0/+2
| | | | | | | | | there are some new CPUID features that are safe for guests to see, as they don't require OS awareness (FPU/ALU related instructions only). Among features for new AMD CPUs there is also the PCLMULQDQ bit, which Intel CPU have already for quite a while. Signed-off-by: Andre Przywara <andre.przywara@amd.com>
* libxc: Update AMD CPU feature flags 0x80000001:ECX for Xen toolsKeir Fraser2011-01-081-14/+19
| | | | | | | This patch syncs-up AMD CPU feature flags 0x80000001:ECX in libxc with the latest Linux kernel. Signed-off-by: Wei Huang <wei.huang2@amd.com>
* x86 hvm: Expose TSC_DEADLINE CPU feature to guests via CPUID.Keir Fraser2010-12-151-0/+1
| | | | Signed-off-by: Wei Gang <gang.wei@intel.com>
* x86 hvm: x2APIC emulationKeir Fraser2010-12-071-0/+1
| | | | | | | | | | | This patch would enable Xen to handle x2APIC MSR accessing of HVM guest, which is faster(avoid decoding of MMIO accessing). The credit comes to Gleb Natapov who complete the work for KVM. Have tested with 4 vcpus guest, with/without x2apic support. From: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x86 hvm: exposes AVX to guest.Keir Fraser2010-11-031-0/+1
| | | | | Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Han Weidong <weidong.han@intel.com>
* # HG changeset patchIan Campbell2010-08-241-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | # User Ian Campbell <ian.campbell@citrix.com> # Date 1282671421 -3600 # Node ID d1dd29a470ef1b9d2c77478a123326036dfe90bb # Parent d7a4adad9c328decbd384d87b23001aea8951b86 tools/libxc, tools/libelf: Relicense under LGPL v2.1 Relicense these two libraries under LGPL v2.1 only except where individual files already included the "or later" provision. Copyright holders have been contacted by Stephen Spector and have all agreed this change. Removed tools/libxc/ia64/aclinux.h since it appeared to be unused. There is a separate, more up to date, copy in xen/include/acpi/platform/aclinux.h which does appear to be used. Clarify the license of MiniOS privcmd.h under the same terms as other tools/include/xen-sys headers. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stephen Spector <stephen.spector@citrix.com> Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
* hvm: Extend the CPUID whitelist to include Intel's AES-NI intructionsKeir Fraser2010-05-261-0/+1
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* x86: Mask X86_FEATURE_XSAVE in cpuid leaf 1, ecx, as we don't allowKeir Fraser2009-03-091-0/+1
| | | | | | | | | | guests to use it (by setting cr4.OSXSAVE). This prevents crashes in pvops kernels, as new versions of Linux try to use this feature. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: support CPUID hypervisor feature bitKeir Fraser2008-11-191-0/+1
| | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: Guest CPUID configuration.Keir Fraser2008-04-251-0/+115
CPUID's replies are now pre-calculated in libxc and given to the hypervisor via a new domctl. There are two parts to this feature: - We can overwrite cpuid's replies. - We can check that a vm is compatible with a host's processor. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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