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author | Liu, Jinsong <jinsong.liu@intel.com> | 2012-09-26 12:14:30 +0200 |
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committer | Liu, Jinsong <jinsong.liu@intel.com> | 2012-09-26 12:14:30 +0200 |
commit | 6fd5f43ad974e8759a9c7bb6c61987fc214f27cc (patch) | |
tree | 83cd481a33d4b22c22dabf74f1a945fa7f521628 /tools/libxc/xc_cpufeature.h | |
parent | e35cd2cce4fe119ef63913f3eb7443b7f5b57d75 (diff) | |
download | xen-6fd5f43ad974e8759a9c7bb6c61987fc214f27cc.tar.gz xen-6fd5f43ad974e8759a9c7bb6c61987fc214f27cc.tar.bz2 xen-6fd5f43ad974e8759a9c7bb6c61987fc214f27cc.zip |
x86: Expose TSC adjust to HVM guest
Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1
indicates TSC_ADJUST MSR 0x3b is supported.
This patch expose it to hvm guest.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'tools/libxc/xc_cpufeature.h')
-rw-r--r-- | tools/libxc/xc_cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index e1772337ad..c464e3a84b 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -128,6 +128,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */ #define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */ +#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */ #define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */ #define X86_FEATURE_HLE 4 /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 5 /* AVX2 instructions */ |