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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-202-3/+35
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| * Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-191-0/+34
| |\ | | | | | | verilog: preserve size of $genval$-s in for loops
| | * Add testcaseEddie Hung2019-12-111-0/+34
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| * | Merge pull request #1571 from YosysHQ/eddie/fix_1570Eddie Hung2019-12-191-3/+1
| |\ \ | | | | | | | | mem_arst.v: do not redeclare ANSI port
| | * | Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1921-66/+755
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| * | Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-181-0/+5
| |\ \ | | | | | | | | add a command to read/modify scratchpad contents
| | * | add assert option to scratchpad commandN. Engelhardt2019-12-162-14/+5
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| | * | add test and make help message more verboseN. Engelhardt2019-12-121-0/+14
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| * | tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-183-3/+232
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| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-183-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1610-53/+228
| |\ \ | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * | Disable RAM16X1D testEddie Hung2019-12-131-17/+17
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| | * | Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
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| | * | Add tests for these new modelsEddie Hung2019-12-121-0/+40
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| | * | Add #1460 testcaseEddie Hung2019-12-121-0/+34
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| | * | Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-129-53/+156
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| * | Add another testEddie Hung2019-12-161-1/+8
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| * | Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * | Add unconditional match blocks for force RAMEddie Hung2019-12-161-0/+9
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| * | Merge blockram testsEddie Hung2019-12-163-47/+81
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| * | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-6/+6
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| * | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-3238/+0
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| * | Merging attribute rules into a single match block; Adding testsDiego H2019-12-153-0/+3373
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| * | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
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| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-2/+2
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| * | Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-122-0/+90
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* | abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-123-23/+136
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| * Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-093-23/+136
| |\ | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| | * unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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| | * ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-3/+5
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| | * Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-2/+2
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| | * Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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| | * Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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| | * Add testcaseEddie Hung2019-12-031-0/+60
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-066-8/+412
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| * | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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| * | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-0/+99
| |/ | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
| * Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-033-2/+301
| |\ | | | | | | Gowin: add and test DFF init values
| | * update testPepijn de Vos2019-12-031-2/+3
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| | * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-10/+12
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| | * attempt to fix formattingPepijn de Vos2019-11-251-138/+138
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| | * gowin: add and test dff init valuesPepijn de Vos2019-11-252-0/+296
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| * | abc9: Fix breaking of SCCsDavid Shah2019-12-011-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-0/+91
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* | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-0/+31
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| * | | Add multiple driver testcaseEddie Hung2019-11-271-0/+31
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