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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 07:34:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 07:34:07 -0800 |
| commit | 23fcfd0adb51f800936b70999a5f95fe59ee7631 (patch) | |
| tree | 37eae708c226d076b8422500f21de0e51f679d07 /tests | |
| parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
| download | yosys-23fcfd0adb51f800936b70999a5f95fe59ee7631.tar.gz yosys-23fcfd0adb51f800936b70999a5f95fe59ee7631.tar.bz2 yosys-23fcfd0adb51f800936b70999a5f95fe59ee7631.zip | |
Make SV2017 compliant courtesy of @wsnyder
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/mem_arst.v | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 9bd38fcb3..88d0553b9 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -7,11 +7,9 @@ module MyMem #( input Clk_i, input [AddrWidth-1:0] Addr_i, input [DataWidth-1:0] Data_i, - output [DataWidth-1:0] Data_o, + output reg [DataWidth-1:0] Data_o, input WR_i); - reg [DataWidth-1:0] Data_o; - localparam Size = 2**AddrWidth; (* mem2reg *) |