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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:47 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:47 -0800 |
| commit | db0003410ff35ab39e3ea408684f600e75c16e78 (patch) | |
| tree | 3a4a9e9d72684660912969b1452f1af667463a75 /tests | |
| parent | 5a00d5578cea91ce84f3d95e6138c85d1a949b89 (diff) | |
| download | yosys-db0003410ff35ab39e3ea408684f600e75c16e78.tar.gz yosys-db0003410ff35ab39e3ea408684f600e75c16e78.tar.bz2 yosys-db0003410ff35ab39e3ea408684f600e75c16e78.zip | |
Accidentally commented out tests
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index b6e105854..4b7716739 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -1,52 +1,52 @@ ### TODO: Not running equivalence checking because BRAM models does not exists ### currently. Checking instance counts instead. -## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -## Anything memory bits < 1024 -> LUTRAM -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 0 t:RAMB18E1 -#select -assert-count 4 t:RAM128X1D -# -## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB36E1 -# -# -#### With parameters +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + + +### With parameters design -reset read_verilog ../common/blockram.v |