| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
Fixes #2321.
|
|
|
|
|
| |
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
|
|
|
|
|
| |
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
|
|
|
|
|
|
|
|
|
| |
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
|
|
|
|
|
|
|
|
|
| |
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
|
| |
|
|
|
|
| |
Fixes #2311.
|
|\
| |
| | |
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
|
| |
| |
| |
| | |
This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
|
| | |
|
|\ \
| |/
|/| |
Avoid generating wires for function args which are constant
|
| | |
|
| | |
|
| | |
|
|/ |
|
|\
| |
| | |
techmap: Add _TECHMAP_CELLNAME_ special parameter.
|
| |
| |
| |
| |
| |
| |
| | |
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
|
|/ |
|
|\
| |
| | |
anlogic: Use dfflegalize.
|
| | |
|
|\ \
| | |
| | | |
Restore #2203 and #2244 and fix parser conflicts
|
| | |
| | |
| | |
| | | |
This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
|
| | |
| | |
| | |
| | | |
This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
|
|/ /
| |
| |
| |
| |
| |
| | |
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
|
| |
| |
| |
| |
| |
| |
| |
| | |
This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15.
This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.
This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3.
This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68.
This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
|
| | |
|
| |
| |
| |
| |
| |
| | |
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
|
|\ \
| | |
| | | |
Add logic type support to parameters
|
| | |
| | |
| | |
| | | |
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
|
| | |
| | |
| | |
| | |
| | |
| | | |
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
|
|/ / |
|
| | |
|
| |
| |
| |
| |
| | |
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
|
| | |
|
| |
| |
| |
| | |
Fixes #2221.
|
| | |
|
| | |
|
| |
| |
| |
| | |
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
|
|/
|
|
|
| |
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
|
|\
| |
| | |
Add dfflegalize pass.
|
| | |
|
|\ \
| | |
| | | |
Signed and macro grammar update
|
| | |
| | |
| | |
| | | |
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
|
|\ \ \
| | | |
| | | | |
Support SystemVerilog Static Cast
|
| | | | |
|
| |_|/
|/| | |
|
| | |
| | |
| | |
| | | |
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
|