aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Collapse)AuthorAgeFilesLines
* Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-4/+16
|\
| * Extend sign extension testsEddie Hung2019-06-201-4/+16
| |
* | Merge remote-tracking branch 'origin/eddie/fix1118' into xc7muxEddie Hung2019-06-201-0/+11
|\ \
| * | Add testEddie Hung2019-06-201-0/+11
| | |
* | | Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-0/+21
|\ \ \ | | |/ | |/|
| * | Remove leftover commentEddie Hung2019-06-201-3/+0
| | |
| * | Add testEddie Hung2019-06-201-0/+24
| |/
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-206-21/+62
|\|
| * Update some .gitignore filesClifford Wolf2019-06-202-3/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-202-0/+6
| |\ | | | | | | | | | towoe-unpacked_arrays
| | * Unpacked array declaration using sizeTobias Wölfel2019-06-192-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
| * | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-192-14/+37
| |\ \ | | | | | | | | Improve handling of initial/default values
| | * | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-247/+0
| | | | | | | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
* | Add a couple more testsEddie Hung2019-06-121-0/+12
| |
* | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵Eddie Hung2019-06-122-53/+0
| | | | | | | | | | | | | | xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2.
* | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-41/+0
| | | | | | | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
* | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-102-0/+53
|\ \
| * | Add testEddie Hung2019-06-102-0/+53
| |/
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-101-1/+6
|\|
| * Add some more commentsEddie Hung2019-06-101-1/+6
| |
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-0728-33/+138
|\|
| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| |
| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| |
| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| |
| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
| |
| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
| |\ | | | | | | elaboration system tasks
| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
| | |\ | | | | | | | | | | | | clifford/pr983
| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-074-3/+42
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-062-0/+41
|\ \ \ \
| * | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
| | | | |
* | | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-0615-0/+512
|\| | | |
| * | | | Fix warningsEddie Hung2019-06-062-3/+3
| | | | |
| * | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
| | | | |
| * | | | Add non exclusive testEddie Hung2019-06-062-0/+56
| | | | |
| * | | | One more and tidy upEddie Hung2019-06-062-6/+28
| | | | |
| * | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
| | | | |
| * | | | Add tests, fix for !=Eddie Hung2019-06-062-0/+78
| |/ / /
| * | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| |/ / | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+4
|\| |
| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
| |\ \ | | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Rename to #23Eddie Hung2019-05-291-3/+3
| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-11 08:39:55 +0000