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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:43:59 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:43:59 -0700 |
commit | d0bbf9e4d4a508179b55a0cc7793d984f3318f7c (patch) | |
tree | 9ca627f8c082b5d25fc79f32961ec492e0531a74 /tests | |
parent | 20119ee50e0cefbcd89275101c8710febd5afd32 (diff) | |
download | yosys-d0bbf9e4d4a508179b55a0cc7793d984f3318f7c.tar.gz yosys-d0bbf9e4d4a508179b55a0cc7793d984f3318f7c.tar.bz2 yosys-d0bbf9e4d4a508179b55a0cc7793d984f3318f7c.zip |
Extend sign extension tests
Diffstat (limited to 'tests')
-rw-r--r-- | tests/various/signext.ys | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/tests/various/signext.ys b/tests/various/signext.ys index ae44a0e06..0c8d671e7 100644 --- a/tests/various/signext.ys +++ b/tests/various/signext.ys @@ -1,7 +1,13 @@ read_verilog -formal <<EOT -module gate(input clk, output [1:0] o); -assign o = 1'bx; +module gate(input clk, output [32:0] o, p, q, r, s, t, u); +assign o = 'bx; +assign p = 1'bx; +assign q = 'bz; +assign r = 1'bz; +assign s = 1'b0; +assign t = 'b1; +assign u = -'sb1; endmodule EOT @@ -10,8 +16,14 @@ proc ## Equivalence checking read_verilog -formal <<EOT -module gold(input clk, output [1:0] o); -assign o = 2'bxx; +module gold(input clk, output [32:0] o, p, q, r, s, t, u); +assign o = {33{1'bx}}; +assign p = {{32{1'b0}}, 1'bx}; +assign q = {33{1'bz}}; +assign r = {{32{1'b0}}, 1'bz}; +assign s = {33{1'b0}}; +assign t = {{32{1'b0}}, 1'b1}; +assign u = {33{1'b1}}; endmodule EOT |