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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
commit | 99ff7b5c8c74371841e74d81b7a0d63cd9487e61 (patch) | |
tree | 72e3b31c807eef5f39c797c8eb3530da98f78980 /tests | |
parent | 31b0dee7f3f12c76b721f2fa8e11c722307abb09 (diff) | |
parent | 3b8f3a93ada563fbae62772b0bf642bb54170954 (diff) | |
download | yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.gz yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.bz2 yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.zip |
Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
Diffstat (limited to 'tests')
-rw-r--r-- | tests/various/signext.ys | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/tests/various/signext.ys b/tests/various/signext.ys index ae44a0e06..0c8d671e7 100644 --- a/tests/various/signext.ys +++ b/tests/various/signext.ys @@ -1,7 +1,13 @@ read_verilog -formal <<EOT -module gate(input clk, output [1:0] o); -assign o = 1'bx; +module gate(input clk, output [32:0] o, p, q, r, s, t, u); +assign o = 'bx; +assign p = 1'bx; +assign q = 'bz; +assign r = 1'bz; +assign s = 1'b0; +assign t = 'b1; +assign u = -'sb1; endmodule EOT @@ -10,8 +16,14 @@ proc ## Equivalence checking read_verilog -formal <<EOT -module gold(input clk, output [1:0] o); -assign o = 2'bxx; +module gold(input clk, output [32:0] o, p, q, r, s, t, u); +assign o = {33{1'bx}}; +assign p = {{32{1'b0}}, 1'bx}; +assign q = {33{1'bz}}; +assign r = {{32{1'b0}}, 1'bz}; +assign s = {33{1'b0}}; +assign t = {{32{1'b0}}, 1'b1}; +assign u = {33{1'b1}}; endmodule EOT |