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* Combine tests to check multiple clock domainsEddie Hung2020-01-021-33/+10
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0210-11/+31
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| * Merge pull request #1606 from YosysHQ/eddie/improve_testsEddie Hung2020-01-019-11/+12
| |\ | | | | | | Fix a few issues in tests/arch/*
| | * Revert insertion of 'reg', leave note behindEddie Hung2020-01-011-1/+2
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| | * Do not do call equiv_opt when no sim model existsEddie Hung2019-12-312-4/+4
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| | * Fix warningsEddie Hung2019-12-312-2/+2
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| | * Call equiv_opt with -multiclock and -assertEddie Hung2019-12-315-5/+5
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| * | Added a test caseMiodrag Milanovic2020-01-011-0/+19
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* | Add some abc9 dff testsEddie Hung2019-12-311-0/+55
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* | Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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* | Remove submod changesEddie Hung2019-12-301-102/+0
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3025-57/+247
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| * Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-3019-60/+61
| |\ | | | | | | Make iopad option default for all xilinx flows
| | * Fix new testsMiodrag Milanovic2019-12-283-6/+6
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| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-285-0/+141
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| | * | Make test without iopadsMiodrag Milanovic2019-12-2817-51/+51
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| | * | Revert "Fix xilinx tests, when iopads are default"Miodrag Milanovic2019-12-2816-40/+40
| | | | | | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c.
| | * | Addressed review commentsMiodrag Milanovic2019-12-211-1/+0
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| | * | Fix xilinx tests, when iopads are defaultMiodrag Milanovic2019-12-2117-42/+44
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| * | | Merge pull request #1599 from YosysHQ/eddie/retry_1588Eddie Hung2019-12-303-0/+48
| |\ \ \ | | | | | | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
| | * | | Add #1598 testcaseEddie Hung2019-12-273-0/+48
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| * / | Update resource countEddie Hung2019-12-281-3/+3
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| * | iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-0/+23
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| * | Add DSP cascade testsEddie Hung2019-12-231-0/+89
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| * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-0/+29
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-202-3/+35
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| * Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-191-0/+34
| |\ | | | | | | verilog: preserve size of $genval$-s in for loops
| | * Add testcaseEddie Hung2019-12-111-0/+34
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| * | Merge pull request #1571 from YosysHQ/eddie/fix_1570Eddie Hung2019-12-191-3/+1
| |\ \ | | | | | | | | mem_arst.v: do not redeclare ANSI port
| | * | Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1921-66/+755
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| * | Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-181-0/+5
| |\ \ | | | | | | | | add a command to read/modify scratchpad contents
| | * | add assert option to scratchpad commandN. Engelhardt2019-12-162-14/+5
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| | * | add test and make help message more verboseN. Engelhardt2019-12-121-0/+14
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| * | tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-183-3/+232
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| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-183-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1610-53/+228
| |\ \ | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * | Disable RAM16X1D testEddie Hung2019-12-131-17/+17
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| | * | Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
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| | * | Add tests for these new modelsEddie Hung2019-12-121-0/+40
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| | * | Add #1460 testcaseEddie Hung2019-12-121-0/+34
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| | * | Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-129-53/+156
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| * | Add another testEddie Hung2019-12-161-1/+8
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| * | Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * | Add unconditional match blocks for force RAMEddie Hung2019-12-161-0/+9
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| * | Merge blockram testsEddie Hung2019-12-163-47/+81
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| * | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-6/+6
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| * | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-3238/+0
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| * | Merging attribute rules into a single match block; Adding testsDiego H2019-12-153-0/+3373
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