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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:40:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 18:40:11 -0800 |
| commit | a59016b146e91311324bc87f9a9437d7ff31d9f2 (patch) | |
| tree | b6bed698cfd7b51c4cb1700cd8657203f078b667 /tests | |
| parent | c082329af33cd428f53f5afbcb51fab8de545090 (diff) | |
| download | yosys-a59016b146e91311324bc87f9a9437d7ff31d9f2.tar.gz yosys-a59016b146e91311324bc87f9a9437d7ff31d9f2.tar.bz2 yosys-a59016b146e91311324bc87f9a9437d7ff31d9f2.zip | |
Fix warnings
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ice40/mul.ys | 2 | ||||
| -rw-r--r-- | tests/arch/ice40/rom.v | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 9891b77d6..b8c3eb941 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog ../common/mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v index 0a0f41f37..c4c677c1e 100644 --- a/tests/arch/ice40/rom.v +++ b/tests/arch/ice40/rom.v @@ -2,7 +2,7 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. */ module top(data, addr); -output [3:0] data; +output reg [3:0] data; input [4:0] addr; always @(addr) begin case (addr) |