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* Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidyEddie Hung2020-05-252-8/+8
|\ | | | | xilinx: tidy up cells_sim.v a little
| * tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* | test: add attribute-before-stmt test from @nakengelhardtEddie Hung2020-05-251-0/+15
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* | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-4/+4
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* | tests: add an generate-else test tooEddie Hung2020-05-251-0/+34
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* | tests: add #2037 testcaseEddie Hung2020-05-251-0/+9
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* xaiger: add testcaseEddie Hung2020-05-241-0/+13
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* Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-0/+28
|\ | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| * tests: attributes before task enableEddie Hung2020-05-141-0/+28
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* | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
| | | | | | | | Fixes #2058.
* | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dffEddie Hung2020-05-186-117/+108
|\ \ | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
| * | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-141-3/+8
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| * | abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
| | | | | | | | | | | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
| * | abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-141-2/+21
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| * | abc9: test to use box file instead of autoEddie Hung2020-05-143-2/+5
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| * | abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-141-5/+7
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| * | abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
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| * | xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
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| * | xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
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* | | Merge pull request #1994 from YosysHQ/eddie/fix_bug1758Eddie Hung2020-05-148-5/+451
|\ \ \ | |/ / |/| | opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
| * | test: update opt_expr_alu testEddie Hung2020-05-081-2/+1
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| * | tests: opt_expr tests that depend on consumexEddie Hung2020-05-081-0/+35
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| * | tests: fsm to use a randomly-generated seedEddie Hung2020-04-241-3/+5
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| * | opt_expr: const_xnor replacement to pad Y with 1'b1Eddie Hung2020-04-241-0/+46
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| * | tests: opt_expr update xnor/xor testsEddie Hung2020-04-242-7/+6
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| * | opt_expr: do not group by X, more fixesEddie Hung2020-04-232-2/+2
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| * | tests: add opt_expr testsEddie Hung2020-04-235-0/+365
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* | | Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-144-0/+93
|\ \ \ | | | | | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * | | test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
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| * | | tests: update/extend task argument testsEddie Hung2020-05-132-2/+35
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| * | | tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
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| * | | Setup tests/verilog properlyEddie Hung2020-05-112-0/+23
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* | | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixesClaire Wolf2020-05-141-0/+13
|\ \ \ | | | | | | | | opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
| * | | opt_clean: improve warning messageEddie Hung2020-05-141-1/+1
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| * | | opt_clean: add init testEddie Hung2020-05-141-0/+13
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* | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-0/+4
|\ \ \ | |/ / |/| | ast: swap range regardless of range_left >= 0
| * | techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-051-1/+0
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| * | test: add failing testEddie Hung2020-05-041-0/+5
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* | | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-0/+46
|\ \ \ | | | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | | Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-062-0/+17
|\ \ \ \ | | | | | | | | | | verilog: allow null gen-if then block
| * | | | verilog: allow null gen-if then blockZachary Snow2020-05-062-0/+17
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* | | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-0/+16
|\ \ \ \ | | | | | | | | | | verilog: set src attribute for primitives
| * | | | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* / / / verilog: fix specify src attributeEddie Hung2020-05-041-0/+6
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* | | Merge pull request #2014 from YosysHQ/claire/fixoptaluClaire Wolf2020-05-031-0/+12
|\ \ \ | | | | | | | | Fix the other "opt_expr -fine" bug introduced in 213a89558
| * | | test: add test for #2014Eddie Hung2020-05-021-0/+12
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* / / tests: aiger test for wire->start_offset != 0Eddie Hung2020-05-022-0/+41
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