Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy | Eddie Hung | 2020-05-25 | 2 | -8/+8 |
|\ | | | | | xilinx: tidy up cells_sim.v a little | ||||
| * | tests: xilinx macc test to have initval, shorten BMC depth for runtime | Eddie Hung | 2020-05-25 | 2 | -8/+8 |
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* | | test: add attribute-before-stmt test from @nakengelhardt | Eddie Hung | 2020-05-25 | 1 | -0/+15 |
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* | | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -4/+4 |
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* | | tests: add an generate-else test too | Eddie Hung | 2020-05-25 | 1 | -0/+34 |
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* | | tests: add #2037 testcase | Eddie Hung | 2020-05-25 | 1 | -0/+9 |
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* | xaiger: add testcase | Eddie Hung | 2020-05-24 | 1 | -0/+13 |
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* | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -0/+28 |
|\ | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts) | ||||
| * | tests: attributes before task enable | Eddie Hung | 2020-05-14 | 1 | -0/+28 |
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* | | Add force_downto and force_upto wire attributes. | Marcelina KoĆcielnicka | 2020-05-19 | 1 | -2/+4 |
| | | | | | | | | Fixes #2058. | ||||
* | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff | Eddie Hung | 2020-05-18 | 6 | -117/+108 |
|\ \ | | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *) | ||||
| * | | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it | Eddie Hung | 2020-05-14 | 1 | -3/+8 |
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| * | | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -5/+29 |
| | | | | | | | | | | | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
| * | | abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ | Eddie Hung | 2020-05-14 | 1 | -2/+21 |
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| * | | abc9: test to use box file instead of auto | Eddie Hung | 2020-05-14 | 3 | -2/+5 |
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| * | | abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too | Eddie Hung | 2020-05-14 | 1 | -5/+7 |
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| * | | abc9: suppress warnings when no compatible + used flop boxes formed | Eddie Hung | 2020-05-14 | 1 | -1/+3 |
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| * | | xilinx: update abc9_dff tests | Eddie Hung | 2020-05-14 | 1 | -18/+45 |
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| * | | xilinx: remove no-longer-relevant test | Eddie Hung | 2020-05-14 | 1 | -91/+0 |
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* | | | Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 | Eddie Hung | 2020-05-14 | 8 | -5/+451 |
|\ \ \ | |/ / |/| | | opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too | ||||
| * | | test: update opt_expr_alu test | Eddie Hung | 2020-05-08 | 1 | -2/+1 |
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| * | | tests: opt_expr tests that depend on consumex | Eddie Hung | 2020-05-08 | 1 | -0/+35 |
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| * | | tests: fsm to use a randomly-generated seed | Eddie Hung | 2020-04-24 | 1 | -3/+5 |
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| * | | opt_expr: const_xnor replacement to pad Y with 1'b1 | Eddie Hung | 2020-04-24 | 1 | -0/+46 |
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| * | | tests: opt_expr update xnor/xor tests | Eddie Hung | 2020-04-24 | 2 | -7/+6 |
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| * | | opt_expr: do not group by X, more fixes | Eddie Hung | 2020-04-23 | 2 | -2/+2 |
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| * | | tests: add opt_expr tests | Eddie Hung | 2020-04-23 | 5 | -0/+365 |
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* | | | Merge pull request #2045 from YosysHQ/eddie/fix2042 | Eddie Hung | 2020-05-14 | 4 | -0/+93 |
|\ \ \ | | | | | | | | | verilog: error if no direction given for task arguments, default to input in SV mode | ||||
| * | | | test: add another testcase as per @nakengelhardt | Eddie Hung | 2020-05-14 | 1 | -0/+25 |
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| * | | | tests: update/extend task argument tests | Eddie Hung | 2020-05-13 | 2 | -2/+35 |
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| * | | | tests: add #2042 testcase | Eddie Hung | 2020-05-11 | 1 | -0/+12 |
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| * | | | Setup tests/verilog properly | Eddie Hung | 2020-05-11 | 2 | -0/+23 |
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* | | | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes | Claire Wolf | 2020-05-14 | 1 | -0/+13 |
|\ \ \ | | | | | | | | | opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically | ||||
| * | | | opt_clean: improve warning message | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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| * | | | opt_clean: add init test | Eddie Hung | 2020-05-14 | 1 | -0/+13 |
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* | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto | Claire Wolf | 2020-05-14 | 1 | -0/+4 |
|\ \ \ | |/ / |/| | | ast: swap range regardless of range_left >= 0 | ||||
| * | | techlibs/common: more robustness when *_WIDTH = 0 | Eddie Hung | 2020-05-05 | 1 | -1/+0 |
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| * | | test: add failing test | Eddie Hung | 2020-05-04 | 1 | -0/+5 |
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* | | | intel_alm: direct LUTRAM cell instantiation | Dan Ravensloft | 2020-05-07 | 1 | -0/+20 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus. | ||||
* | | | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 1 | -0/+46 |
|\ \ \ | | | | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset | ||||
| * | | | Bugfix in partsel.v signed indices test cases | Claire Wolf | 2020-05-02 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
| * | | | Add tests based on the test case from #1990 | Claire Wolf | 2020-05-02 | 1 | -0/+46 |
| | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 2 | -0/+17 |
|\ \ \ \ | | | | | | | | | | | verilog: allow null gen-if then block | ||||
| * | | | | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 2 | -0/+17 |
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* | | | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 1 | -0/+16 |
|\ \ \ \ | | | | | | | | | | | verilog: set src attribute for primitives | ||||
| * | | | | tests: add tests for primitives' src | Eddie Hung | 2020-05-04 | 1 | -0/+16 |
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* / / / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -0/+6 |
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* | | | Merge pull request #2014 from YosysHQ/claire/fixoptalu | Claire Wolf | 2020-05-03 | 1 | -0/+12 |
|\ \ \ | | | | | | | | | Fix the other "opt_expr -fine" bug introduced in 213a89558 | ||||
| * | | | test: add test for #2014 | Eddie Hung | 2020-05-02 | 1 | -0/+12 |
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* / / | tests: aiger test for wire->start_offset != 0 | Eddie Hung | 2020-05-02 | 2 | -0/+41 |
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