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| * | | | Add nonexcl case test, comment out two othersEddie Hung2019-06-072-22/+57
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| * | | | Add @cliffordwolf freduce testcaseEddie Hung2019-06-072-0/+30
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| * | | | Add nonexclusive test from @cliffordwolfEddie Hung2019-06-072-0/+28
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| * | | | Another muxpack testEddie Hung2019-06-072-0/+32
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| * | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
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| * | | | Fix warningsEddie Hung2019-06-062-3/+3
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| * | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
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| * | | | Add non exclusive testEddie Hung2019-06-062-0/+56
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| * | | | One more and tidy upEddie Hung2019-06-062-6/+28
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| * | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
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| * | | | Add tests, fix for !=Eddie Hung2019-06-062-0/+78
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* | | | | Add tests/various/abc9.{v,ys} with SCC testEddie Hung2019-06-242-0/+19
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* | | | Merge pull request #1108 from YosysHQ/clifford/fix1091Eddie Hung2019-06-211-1/+140
|\ \ \ \ | | | | | | | | | | Add support for partial matches to muxcover
| * | | | Missing a `clean` and `opt_expr -mux_bool` in testEddie Hung2019-06-201-0/+4
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| * | | | Add testEddie Hung2019-06-201-1/+136
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* | | | Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-212-0/+114
|\ \ \ \ | | | | | | | | | | Improve shregmap to handle case where first flop is common to two chains
| * | | | Add shregmap -tech xilinx testEddie Hung2019-06-122-2/+63
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| * | | | Add testEddie Hung2019-06-102-0/+53
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* | | | Extend sign extension testsEddie Hung2019-06-201-4/+16
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* | | | Remove leftover commentEddie Hung2019-06-201-3/+0
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* | | | Add testEddie Hung2019-06-201-0/+24
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* | | Update some .gitignore filesClifford Wolf2019-06-201-1/+2
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
|\ \ | |/ |/| | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Fix initEddie Hung2019-05-241-27/+27
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* | Fix typosEddie Hung2019-05-241-6/+6
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* | Add more testsEddie Hung2019-05-242-20/+41
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* | Call procEddie Hung2019-05-241-1/+1
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* | Fix duplicate driverEddie Hung2019-05-241-15/+15
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* | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
|\ \ | | | | | | Add specify parser
| * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | More testingEddie Hung2019-05-032-2/+5
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| * | Fix spacingEddie Hung2019-05-031-6/+6
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| * | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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* / Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
|\ | | | | Add pmux2shiftx command
| * Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix testsClifford Wolf2019-04-211-0/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-151-3/+2
| | | | #931)"
* Add default entry to testcaseEddie Hung2019-04-111-2/+3
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* Address requested changes - don't require non-$ name.Jim Lawson2019-02-222-4/+7
| | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
* Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-192-1/+65
| | | | Add simple test.
* Modified errors into warningsUdi Finkelstein2018-06-051-4/+38
| | | | No longer false warnings for memories and assertions
* reg_wire_error test needs the -sv flag so it is run via a script so it had ↵Udi Finkelstein2018-06-052-0/+41
| | | | to be moved out of the tests/simple dir that only runs Verilog files
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-20 12:02:07 +0000