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authorEddie Hung <eddie@fpgeh.com>2019-06-06 12:44:06 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-06 12:44:06 -0700
commit705388eb24022d2a310ae72cd81e67a2f0ce7586 (patch)
treed6c5b4e0b668978d9f14a2d2e4f3ba8facff1345 /tests/various
parent83450a94898321a239f67f92e05fb9a246f4dd6d (diff)
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Add non exclusive test
Diffstat (limited to 'tests/various')
-rw-r--r--tests/various/muxpack.v20
-rw-r--r--tests/various/muxpack.ys36
2 files changed, 56 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index c2c2537a0..e847fef27 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -64,4 +64,24 @@ always @* begin
end
endmodule
+module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+ if (s == 0) o <= i[0*W+:W];
+ else if (s == 1) o <= i[1*W+:W];
+ else if (s == 2) o <= i[2*W+:W];
+ else if (s == 3) o <= i[3*W+:W];
+ else if (s == 0) o <= {W{1'b0}};
+ else o <= {W{1'bx}};
+endmodule
+module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+ o <= {W{1'bx}};
+ if (s == 0) o <= i[0*W+:W];
+ if (s == 1) o <= i[1*W+:W];
+ if (s == 2) o <= i[2*W+:W];
+ if (s == 3) o <= i[3*W+:W];
+ if (s == 4) o <= i[4*W+:W];
+ if (s == 0) o <= i[2*W+:W];
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index a967ddfef..178860b88 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,6 +6,7 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
@@ -20,6 +21,7 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
@@ -34,6 +36,7 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
@@ -48,6 +51,7 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
@@ -62,6 +66,7 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
@@ -76,6 +81,37 @@ design -save gold
muxpack
opt
stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_4_1_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold