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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 14:01:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 14:01:42 -0700 |
| commit | 0a66720f6f67b087fe6342d01d45944506240942 (patch) | |
| tree | be3a4976cb6a57e18adaf2a93a038bc181aa7e88 /tests/various | |
| parent | ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 (diff) | |
| download | yosys-0a66720f6f67b087fe6342d01d45944506240942.tar.gz yosys-0a66720f6f67b087fe6342d01d45944506240942.tar.bz2 yosys-0a66720f6f67b087fe6342d01d45944506240942.zip | |
Fix warnings
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/muxpack.v | 4 | ||||
| -rw-r--r-- | tests/various/muxpack.ys | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index fe0150532..7c189fff8 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -74,7 +74,7 @@ always @* else o <= {W{1'bx}}; endmodule -module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; if (s == 0) o <= i[0*W+:W]; @@ -86,7 +86,7 @@ always @* begin end endmodule -module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; case (s) diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 4dcb9ed89..0c5b82818 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top mux_case_unbal_7_7 +hierarchy -top mux_case_unbal_8_7 prep design -save gold muxpack |