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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 12:12:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 12:12:11 -0700 |
| commit | 1da12c5071a738504d22e68d66cab7c5c5afb07e (patch) | |
| tree | 07f7190f8c76d4edda9e4caf569d23c300e96b53 /tests/various | |
| parent | e263bc249b905195120fbc074c6f80d03fb21cf8 (diff) | |
| download | yosys-1da12c5071a738504d22e68d66cab7c5c5afb07e.tar.gz yosys-1da12c5071a738504d22e68d66cab7c5c5afb07e.tar.bz2 yosys-1da12c5071a738504d22e68d66cab7c5c5afb07e.zip | |
Add @cliffordwolf freduce testcase
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/muxpack.v | 13 | ||||
| -rw-r--r-- | tests/various/muxpack.ys | 17 |
2 files changed, 30 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f3c25db8d..d45ce4045 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select ( if (z) o = d; end endmodule + +module cliffordwolf_freduce ( + input wire [1:0] s, + input wire a, b, c, d, + output reg [3:0] o +); + always @* begin + o = {4{a}}; + if (s == 0) o = {3{b}}; + if (s == 1) o = {2{c}}; + if (s == 2) o = d; + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 7c3fe5070..afdacdf30 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -178,3 +178,20 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top cliffordwolf_freduce +prep +design -save gold +proc; opt; freduce; opt +write_verilog -noexpr -norename +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |