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* Merge pull request #2028 from zachjs/masterEddie Hung2020-05-062-0/+17
|\ | | | | verilog: allow null gen-if then block
| * verilog: allow null gen-if then blockZachary Snow2020-05-062-0/+17
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* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-0/+16
|\ \ | | | | | | verilog: set src attribute for primitives
| * | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* / verilog: fix specify src attributeEddie Hung2020-05-041-0/+6
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* test: add test for #2014Eddie Hung2020-05-021-0/+12
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* Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
|\ | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share
| * tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
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* | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
|\ \ | | | | | | design: -import to not count black/white-boxes as candidates for top
| * | design: add testEddie Hung2020-04-162-5/+22
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* | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
|\ \ | | | | | | sim: Fix handling of constant-connected cell inputs at startup
| * | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
| | | | | | | | Fixes #1821.
* | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
|\ \ | | | | | | Improved rewrite code for writing to bit slice
| * | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
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| * | Simplify test case scriptEddie Hung2020-04-201-30/+17
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| * | Modifications of tests as per Eddie's requestdiego2020-04-2013-0/+1237
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* | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
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* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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* tests: add a quick plugin testEddie Hung2020-04-093-0/+22
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* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-191-0/+33
| | | | Fixes #1781.
* Add test for `exec` command.Alberto Gonzalez2020-03-161-0/+6
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-0/+24
|\ | | | | refixed parsing of constant with comment between size and value
| * Add regression tests for new handling of comments in constantsMarcus Comstedt2020-03-142-0/+24
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* | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-0/+8
|\ \ | | | | | | Set AST node source location in more parser rules.
| * | verilog: add testEddie Hung2020-03-111-0/+8
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* | | Added back tests for loggerMiodrag Milanovic2020-03-134-0/+24
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* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-0/+14
|\ \ | |/ |/| deminout: Don't demote inouts with unused bits
| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-0/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+2
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
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* | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-0/+124
|\ \ | | | | | | submod: several bugfixes
| * \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-017-11/+98
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| * | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
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* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-19/+1
|\ \ \ \ | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | Cleanup testsEddie Hung2020-02-272-19/+1
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* / | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-0/+30
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* | | clean: ignore specify-s inside cells when determining whether to keepEddie Hung2020-02-191-1/+20
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* | | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-0/+7
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* | | verilog: improve specify support when not in -specify modeEddie Hung2020-02-132-3/+1
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* | | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-0/+6
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* | | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-0/+7
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* | | verilog: fix $specify3 checkEddie Hung2020-02-131-0/+7
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* | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-0/+5
|\ \ \ | | | | | | | | Fix crash on wire declaration with delay
| * | | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
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* | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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